Vertical double-diffused metal oxide semiconductor field effect transistor having semi-insulating polysilicon layer

Abstract

The invention provides a vertical double-diffused metal oxide semiconductor field effect transistor (VDMOS) having a semi-insulating polysilicon layer (SIPOS). The VDMOS is mainly characterized in that an SIPOS filling layer is formed on the side wall of a device drift region, and two ends of the SIPOS filling layer are connected with a gate end and a drain end of the VDMOS. On one hand, since the SIPOS has uniform resistivity, the SIPOS has a uniform electric field when the VDMOS is turned off. According to an electric displacement continuity equation, an electric field on the device drift region is modulated by means of the uniform electric field on the SIPOS and becomes more uniform, and the SIPOS layer enhances the depletion of the device drift region of the VDMOS, thus doping concentration of the device drift region is increased, and the VDMOS has low on-resistance when being turned on; on the other hand, since a potential difference exists between the surfaces of the SIPOS layer and the device drift region, the device drift region has majority carrier accumulation, thereby further decreasing the on-resistance of the VDMOS.

Description

technical field [0001] The invention relates to the field of semiconductor devices, in particular to a trench (Trench) type vertical double-diffused metal oxide semiconductor field effect transistor. Background technique [0002] The development of power semiconductor devices has brought electronic products into a new stage. Power MOSFET is a multi-subconductive device, which has the advantages of fast switching speed, high input impedance, easy driving, and no secondary breakdown phenomenon. In 1985, a trench (Trench) MOS structure was proposed by D.Ueda et al. The U-shaped groove structure makes the conduction channel of the device change from horizontal to vertical, which effectively eliminates the resistance of JFET, greatly increases the original cell density, and improves the current handling capacity of the device. However, in the field of high-voltage applications of power devices, as the breakdown voltage of the device increases, the thickness of the power VDMOS e...

AI Technical Summary

Problems solved by technology

However, in the field of high-voltage applications of power devices, as the breakdown voltage of the device increases, the thickness of the power VDMOS epitaxial layer increases continuously, and the doping concentration of the drift region gradually decreases, resulting in the on-resistance of the device decreasing with 2.5% of the breakdown voltage of the device. time increases sharply, which increases the conduction loss of the device

Images