Silicon-on-insulator (SOI) six-transistor static random access memory (SRAM) unit and fabrication method thereof
A six-transistor and manufacturing method technology, applied in the field of memory design and manufacturing, can solve the problems of large occupied area of SRAM cells, weak anti-noise capability, poor stability, etc., and achieve the effects of simple manufacturing process, improved anti-noise capability, and shortened cycle.
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Embodiment 1
[0096] The present invention provides a SOI six-transistor SRAM unit, please refer to figure 1 , shown as a schematic circuit diagram of the SOI six-transistor SRAM cell, including:
[0097] The first inverter 1 is composed of a first PMOS transistor 101 and a first NMOS transistor 102;
[0098] The second inverter 2 is composed of a second PMOS transistor 201 and a second NMOS transistor 202;
[0099] The acquisition transistor 3 is composed of a third NMOS transistor 301 and a fourth NMOS transistor 302; the source of the third NMOS transistor 301 is connected to the output terminal of the first inverter and the input of the second inverter terminal, the gate is connected to the word line WL of the memory, and the drain is connected to the bit line BL of the memory; the source of the fourth NMOS transistor 302 is connected to the output end of the second inverter and the first inverter The gate is connected to the word line of the memory, and the drain is connected to the ...
Embodiment 2
[0112] The present invention also provides a method for manufacturing an SOI six-transistor SRAM unit, comprising the following steps:
[0113] Step S1 is first performed: provide an SOI substrate including a back substrate, an insulating buried layer, and a top layer of silicon in sequence from bottom to top, and form a shallow trench isolation structure in the top layer of silicon to define an active region.
[0114] As an example, such as Figure 7 As shown, four active regions 20a, 20b, 20c, and 20d are defined. These four active regions are arranged in parallel in turn, and shallow trenches are formed around each active region, and the shallow trenches are filled with insulating materials to form shallow trenches. isolation structure. In this embodiment, the insulating material is silicon dioxide.
[0115] Then execute step S2: as Figure 8 As shown, an N well 30, a first P well 40a, and a second P well 40b are fabricated in the top layer silicon according to the posit...
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