Optimization method for optimizing environment stability of etching cavity

Abstract

The present invention provides an optimization method for optimizing the environment stability of an etching cavity. The method comprises the steps of replacing a coating member on the inner wall of the etching cavity; subjecting the coating with the replaced coating member to the micro-roughening treatment; and subjecting the coating member on the inner wall of the etching cavity to the wafer-free automatic dry-etching and cleaning process. During the above process, silicon-oxygen compounds are adsorbed on the coating surface of the coating member and the adsorption is in a saturated state. According to the technical scheme of the invention, the environment drifting phenomenon of the etching cavity, caused by the replacement of new components, is improved. Meanwhile, the environment stability of the etching cavity is improved, so that the key dimension stability of the etching process is improved. Moreover, the electrical performances of wafers and the yield of products are improved, and the rejection rate is reduced.

Description

Technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for optimizing the environmental stability of an etching cavity. Background technique [0002] As integrated circuit technology enters the era of ultra-large-scale integrated circuits, the process size of integrated circuits is developing toward 65nm and smaller structures, and higher and more detailed technical requirements are put forward for wafer manufacturing processes. Among them, the key size of the polysilicon gate of the wafer has increasingly become a key parameter of polysilicon etching. The key size of the polysilicon gate determines the operating performance of the device gate circuit and is more and more sensitive to the influence of the yield of the wafer. [0003] At present, in the large-scale wafer manufacturing process, with the continuous increase in the number of wafers processed, the internal environment of the etching cavity will chang...

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Problems solved by technology

[0005] At present, in the manufacturing process of 65nm and smaller sizes, after the maintenance of the etching chamber, in order to test the stability of the etching chamber, it is necessary to first operate one or several wafers to test the etching chamber before mass production According to the test results, it is determined whether it is necessary to adjust the etching time of the hard mask layer lateral modification (HM trim), but the etching chamber maintenance replaces the inner wall parts of the etching chamber (with Y2O3 coating on the surface) It is not a new part, but a cleaned inner wall part that was removed after the last maintenance. These inner wall parts with different RF hours show different differences due to the roughness of their surface with different RF hours. , after the WAC operation, the ability of the polymer adsorbed on the surface of the inner wall device is also different. Or the impact of several test wafers is also different, and directly adjusting the polysilicon etching process parameters according to the advanced process control (Advanced process control, referred to as APC) system currently used in the polysilicon gate etching process will make a piece of priority work Or a few wafers have high operational risks, mainly manifested in the drift of the key dimensions of the polysilicon gate, which will eventually lead to problems such as the electrical parameters of the wafers failing to meet product specifications and product yields falling

[0006] It was proposed to quantitatively control the critical dimensions after polysilicon gate etching based on the thickness of the deposited silicon-oxygen polymer in the WAC process. This method overcomes the influence of free particles on the atmosphere of the polysilicon etching chamber in the prior art. It is difficult to quantitatively control the critical dimension of the polysilicon gate, but how to control the stability of the critical dimension of the polysilicon gate after each etching chamber maintenance cannot be well solved

[0007] The above method does not solve the problem of offset of critical dimensions and the introduction of metal ion contamination during the maintenance of the etching chamber in the prior art, and cannot quantitatively adjust the critical dimensions and metal ion contamination after the maintenance of the etching chamber. The control of the ion source, at the same time, it is difficult to quickly and accurately find the entry point of the problem when there is a problem with the critical dimension, which affects the electrical performance of the wafer and the product yield

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