LDMOS with low conduction resistance and relatively low total gate charge and preparation method for LDMOS

Abstract

The invention provides an LDMOS with low conduction resistance and relatively low total gate charge. The LDMOS comprises a source, a gate, a drain and a metal shielding layer, wherein the metal shielding layer comprises a first metal shielding layer crosses over the upward side of the gate; one end of the first metal shielding layer is positioned below and in contact with the source while a certain distance is formed between the other end of the first metal shielding layer and the drain; the thickness of an insulating dielectric layer between the first metal shielding layer and the gate is used for adjusting the value of a coupling capacitance; and the distance between the other end of the first metal shielding layer and the drain is used for adjusting an electric field between the source and the drain. The technological steps provided by the invention are compatible with a standard CMOS process, an extra mask and a special machine platform are not required; instead, only the ILD thickness and the extension distances of different metal shielding layers M0 need to be adjusted through the process, so that the coupling capacitance is formed between the metal shielding layer and the oxide or silicon nitride SiN and other mediums of the drain; and therefore, different drain electric field coupling is realized, the gate is protected from high voltage impact, and optimization of different voltage devices is realized.

Description

technical field [0001] The invention relates to an LDMOS (Laterally Diffused Metal Oxide Semiconductor) capable of realizing low on-resistance (Ron) and lower total gate charge (Qg) and its preparation process. Background technique [0002] Traditional LDMOS uses an additional mask as a metal shielding layer, such as figure 1 M1 layer in . figure 1 In the M1 layer, metal W, WSi or Ti+TiN is used. [0003] However, since the shielding metal is not compatible with standard CMOS (Complementary Metal Oxide Semiconductor), very few high-speed LDMOSs can provide gate shielding on standard MOS lines. This requires adding an additional mask to reduce the on-resistance and total gate charge, and requires a special machine for implantation. Contents of the invention [0004] The object of the present invention is to provide a LDMOS with low on-resistance and lower total gate charge and its preparation process, which solves the technical problem of high on-resistance and total gat...

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Problems solved by technology

[0004] The object of the present invention is to provide a LDMOS with low on-resistance and lower total gate charge and its preparation process, which solves the technical problem of high on-resistance and total gate charge of the existing LDMOS, thereby protecting the gate from Under the impact of high voltage, it achieves very low on-resistance and total gate charge, and has a good effect of suppressing high electric field

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