Vertical channel heterostructure field-effect transistor and preparation method thereof

Abstract

The invention discloses a vertical channel heterostructure field-effect transistor (VC-HFET) and a preparation method thereof. The heterostructure field-effect transistor comprises a source electrode, a drain electrode, a grid electrode and at least one heterostructure channel, wherein the axis of the heterostructure channel is fundamentally vertical to a selected plane; the heterostructure channel is positioned in a heterostructure; the heterostructure comprises a second semiconductor and a first semiconductor arranged around the second semiconductor, the energy gap of the first semiconductor is greater than that of the second semiconductor, and two-dimensional electron gas or two-dimensional hole gas is formed in the heterostructure channel; the source electrode is electrically connected with the drain electrode through the two-dimensional electron gas or the two-dimensional hole gas; and the grid electrode is distributed between the source electrode and the drain electrode. The heterostructure field-effect transistor disclosed by the invention has the advantages of being good in grid-control capacity, high in work efficiency, low in process difficulty, easy to manufacture, high in rate of finished products and the like.

Description

technical field [0001] The invention relates to a semiconductor device, in particular to a vertical channel-based heterojunction field-effect transistor (Vertical Channel Heterostructure Field-effect Transistor, VC-HFET) device and a preparation method thereof. Background technique [0002] With the development of microelectronics technology, CMOS devices and integrated circuits have entered the so-called post-Moore era, that is, the development of integrated circuits has gradually deviated from the curve of "Moore's Law". Especially the "short heterojunction channel effect" and "DIBL effect" (DrainInduced Barrier Lowering, The potential barrier introduced by the drain terminal is lowered) and the source-drain direct tunneling makes it more and more difficult to reduce the size of the device. And because the gate length is shortened, the gate control ability is reduced, the subthreshold swing of the device and the switch current ratio are reduced, and a series of problems s...

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Problems solved by technology

For another example, the vertical channel device of Si can first form a multi-layer structure with different doping types and then etch to form a vertical channel structure, but this undoubtedly increases the complexity of the process, and the Si material system due to its material properties Due to the limitation, the performance in terms of high pressure resistance, high temperature resistance and radiation resistance is not ideal

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