Method of preparing ultrathin silicide

Abstract

The invention discloses a method of preparing an ultrathin silicide. The method comprises the following steps: (1) preparing an insertion stop layer on a silicon substrate; (2) preparing a metal layer on the stop layer; (3) annealing the structure obtained in step (2) to make metal in the metal layer diffuse across the insertion stop layer and react with silicon to form an ultrathin silicide; and (4) removing excess metal and the insertion stop layer to get an ultrathin silicide. Through the method, an ultrathin silicide less than 2nm can be prepared. The amount of metal driven in is controlled by changing the thickness of the insertion stop layer, so that silicides made of the same metal but of different phases and thicknesses can be obtained. The process is of high controllability. The formed ultrathin silicide has the characteristics of low resistivity, low Schottky barrier, good uniformity, and good smoothness. Compared with the conventional ultrathin silicide preparation method, the meal deposition process window is widened greatly. The method is completely compatible with a bulk silicon CMOS process. The process is simple and low in cost.

Description

technical field [0001] The invention belongs to the technical field of ultra-large-scale integrated circuit manufacturing, and relates to a method for preparing ultra-thin metal silicide in integrated circuits. Background technique [0002] When the process node of integrated circuits advances to 14nm, traditional planar transistors face many problems such as serious short-channel effects and performance degradation, and can no longer meet the requirements of proportional scaling. Multi-gate devices enhance the coupling ability between the gate and the channel by increasing the number of gates, which has become the mainstream of logic devices in the post-Moore era. Due to the continuous shrinking of the size, the proportion of the source-drain resistance in the total resistance is increasing, and the on-state current of multi-gate devices is seriously degraded. Therefore, reducing the source-drain parasitic resistance is very important for optimizing the on-state performance...

AI Technical Summary

Problems solved by technology

However, the former has higher requirements on the thickness and uniformity of the deposited metal; the characteristic of the latter is that in order to form ultra-thin silicide, the temperature and time of the initial annealing must be strictly controlled to control the amount of metal driven in. The temperature of the secondary annealing should not be too high, otherwise it is easy to cause different annealing temperatures in different regions, which will lead to interface peaks

These shortcomings limit their application in source-drain engineering of large-scale integrated circuits

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