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Reconfigurable arithmetic unit supporting multiple working modes and working modes thereof

A computing unit and working mode technology, applied in computing, computers, multi-programming devices, etc., can solve the problems of high computing efficiency, low ASIC computing efficiency, lack of versatility, etc., achieve strong flexibility, and realize computing priority The effect of management, ease of integration and use

Active Publication Date: 2016-11-23
HEFEI UNIV OF TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

ASIC is designed for specific applications, with high computing efficiency but not universal; GPP is used for general computing and has strong flexibility, but compared with ASIC, the computing efficiency is low

Method used

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  • Reconfigurable arithmetic unit supporting multiple working modes and working modes thereof
  • Reconfigurable arithmetic unit supporting multiple working modes and working modes thereof
  • Reconfigurable arithmetic unit supporting multiple working modes and working modes thereof

Examples

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Embodiment Construction

[0055] In the implementation of this example, a reconfigurable computing unit that supports multiple working modes is mounted on such as figure 1 On any two routing nodes of the on-chip network of the shown on-chip multi-core computing system, the data exchange with the on-chip network is completed through the local interface of the on-chip network; figure 2 A structural block diagram of the present invention is given, and the reconfigurable computing unit includes: a control layer, a computing layer and a storage layer;

[0056] The control layer includes: state layer interface, configuration layer interface, data layer interface, address generator and controller;

[0057] The operation layer includes: operator;

[0058] The storage layer includes: source operand cache unit, destination operand cache unit;

[0059] Both the source operand cache unit and the destination operand cache have a cache threshold. The cache threshold is based on the scale of the computing system’s...

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PUM

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Abstract

The invention discloses a reconfigurable unit supporting multiple working modes and the working modes thereof. The reconfigurable unit is characterized by comprising a control layer, an arithmetic layer and a storage layer; the control layer comprises a state layer interface, a configuration layer interface, a data layer interface, an address generator and a controller; the arithmetic layer comprises an arithmetic device; the storage layer comprises a source operand cache unit and a destination operand cache unit. The working modes of the reconfigurable arithmetic unit comprise the storage arithmetic mode, the pulse arithmetic mode and the stream arithmetic mode, and higher flexibility is provided for algorithm mapping of a computing system. When task mapping is carried out in the computing system, the specific working modes of the reconfigurable arithmetic unit can be selected according to specific features and the bottleneck of the algorithm to be mapped and in combination with specific conditions of network communication and storage bandwidth in the computing system, therefore, the arithmetic throughput capacity and network communication and storage access pressure are considered, and the working efficiency of the whole system is improved.

Description

technical field [0001] The invention relates to the field of high-density computing and digital signal systems, in particular to a reconfigurable computing unit used in an on-chip multi-core computing system and its working method. Background technique [0002] Application-specific integrated circuits (ASICs) and general-purpose processors (GPPs) are two common types of data processing hardware. ASIC is designed for specific applications, with high computing efficiency but not universal; GPP is used for general computing and has strong flexibility, but its computing efficiency is lower than that of ASIC. Reconfigurable computing has achieved a balance between the high efficiency of ASIC and the versatility of GPP. On the basis of ensuring generality in a certain field, it has achieved higher efficiency than GPP. It is a common computing system in today's multi-core computing systems. Computing power organization form. [0003] Multi-core technology has become the mainstrea...

Claims

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Application Information

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IPC IPC(8): G06F9/50G06F15/173
CPCG06F9/5066G06F15/17306G06F2209/5022
Inventor 宋宇鲲李浩洋张多利
Owner HEFEI UNIV OF TECH
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