Three-valued static random access memory cell realized by utilization of carbon nanotube field effect transistor

Abstract

The invention discloses a three-valued static random access memory cell realized by the utilization of a carbon nanotube field effect transistor. The three-valued static random access memory cell comprises a first CNFET tube, a second CNFET tube, a third CNFET tube, a fourth CNFET tube, a fifth CNFET tube, a sixth CNFET tube, a seventh CNFET tube, a eighth CNFET tube, a ninth CNFET tube, a tenth CNFET tube, a eleventh CNFET tube and a twelfth CNFET tube. The first CNFET tube, the second CNFET tube, the fourth CNFET tube, the fifth CNFET tube, the seventh CNFET tube, the ninth CNFET tube, the tenth CNFET tube and the eleventh CNFET tube are N-type CNFET tubes. The third CNFET tube, the sixth CNFET tube, the eighth CNFET tube and the twelfth CNFET tube are P-type CNFET tubes. The three-valued static random access memory cell has advantages of fast read-write speed, high stability of read data, small wiring area, low power consumption and large memory capacity.

Description

technical field [0001] The invention relates to a static random storage unit, in particular to a three-value static random storage unit realized by using a carbon nanometer field effect transistor. Background technique [0002] With the development of CMOS technology and integrated circuit technology, the miniaturization of circuits brings great convenience to people's lives, and at the same time puts forward higher requirements for characteristics such as high integration and low power consumption. Especially for the issue of high integration, due to the reduction of feature size, the number of integrated components per unit chip area has increased sharply, and the feature size of integrated circuits has entered the nanometer level. In VLSI (Very Large Scale Integration, VLSI), more than 70% of the silicon area is used for wiring, which further restricts the improvement of integration. At the nanometer level, problems such as gate delay, interconnect crosstalk, and power c...

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Problems solved by technology

But there is following problem in this SRAM cell: one, when writing operation, bit line BL and It is difficult to change the logic value stored in the cross-coupled inverter by pre-charging to the corresponding level. It is necessary to adjust the parameters of each CMOS tube, and it takes a while to write the data, which reduces the speed of writing data; 2. During the read operation, When WL is high, the bit line BL and precharged to a high voltage affects nodes Q and Therefore, during the read process, the internally stored data may be destroyed, and the stability of the read data is poor; 3. Data is read and written through the bit lines BL and This leads to an increase in the wiring area of ​​the static random storage unit; four, high power consumption; five, small storage capacity

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