Sealing ring of chip

Abstract

The invention provides a sealing ring of a chip. The sealing ring comprises one or more sealing units; each sealing unit comprises a first metal wiring layer, a second metal wiring layer, an interlayer dielectric layer, and one or more via hole groups; the first metal wiring layer surrounds the chip; the first metal wiring layer includes a first metal portion and a first dielectric material portion which are insulated from each other; the second metal wiring layer is opposite to the first metal wiring layer; the second metal wiring layer includes a second metal portion and a second dielectric material portion which are insulated from each other; the interlayer dielectric layer is arranged between the first metal wiring layer and the second metal wiring layer; the one or more via hole groups surround the chip, are arranged in the interlayer dielectric layer and are connected with the first metal portion and the second metal portion; and each via hole group includes a plurality of via holes which are independent from each other. A via hole formation mechanical stress breaks through the obstruction of an adhesion force between the first metal portion, the second metal portion and the via holes, so that the problem of delamination of the edge of the chip can be alleviated; and the rigidness of the via holes is decreased, so that the deformation ability of the via holes can be increased, and therefore, the delamination of the edge of the chip can be effectively prevented.

Description

technical field [0001] The present application relates to the technical field of semiconductor manufacturing, in particular, to a sealing ring of a chip. Background technique [0002] In a semiconductor manufacturing process, a semiconductor chip including a semiconductor active device and an interconnection structure disposed on the device can be formed on a semiconductor substrate through processes such as photolithography, etching, and deposition. Usually, multiple chips can be formed on a wafer, and finally these chips are cut off from the wafer for packaging process to form an integrated circuit area. During the process of dicing the chip, the stress generated by the dicing knife will cause damage to the edge of the chip, and even cause the chip to collapse. In the prior art, in order to prevent the chip from being damaged during dicing, a sealing ring is provided around the active device area of ​​the chip, which can block the stress generated by the dicing knife and ...

AI Technical Summary

Problems solved by technology

[0005] The purpose of this application is to provide a chip sealing ring to solve the problem of easy delamination of the edge of the chip in the scribing process of the prior art

Images