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An AES Algorithm-Oriented Anti-Power Attack Method Based on Random Delay

A random delay and anti-power consumption technology, applied in countermeasures against encryption mechanisms, encryption devices with shift registers/memory, digital transmission systems, etc., can solve the problem of large impact on performance and hardware resource overhead, high implementation cost, Solve problems such as cumbersome solutions, achieve low cost of anti-attack, good anti-attack effect, and good compatibility

Active Publication Date: 2019-01-29
SOUTHEAST UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, some existing technologies are expensive to implement and have a great impact on performance and hardware resource overhead; some anti-attack methods have limitations, and it is difficult to resist preprocessing methods such as elastic alignment; EDA tool flow

Method used

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  • An AES Algorithm-Oriented Anti-Power Attack Method Based on Random Delay
  • An AES Algorithm-Oriented Anti-Power Attack Method Based on Random Delay
  • An AES Algorithm-Oriented Anti-Power Attack Method Based on Random Delay

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Embodiment Construction

[0021] The technical solution of the present invention will be further introduced below in combination with specific embodiments.

[0022] The traditional AES algorithm consists of 3 parts, which are the initial key addition, 9 rounds of the same round operation, and the 10th round of final transformation. Each round requires a round key to complete the key addition operation, and there are eleven subkeys in total, denoted as Kn (n=0,...,10). The subkey is obtained by expanding the initial key. The 9-cycle round operation in the middle of the AES algorithm includes four operations: byte replacement, row shift, column mixing, and key addition. The transformation at the end of the tenth round includes three operations: byte replacement, row shift and key addition. AES will generate an intermediate value data at the end of each round, which can be recorded as Dn (n=0,...,10) and stored in the register, where D10 is the ciphertext output.

[0023] Such as figure 1 As shown, ta...

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Abstract

The invention discloses an AES-algorithm-oriented power analysis attack resistant method based on random time delay. A random number generator and a random time delay module are added in an AES algorithm; a plurality of different time delay paths are provided between a register and a wheel operation module; one path is randomly selected through the random number generated by the random number generator, so that the power consumption generation time point generated by the wheel operation module trends to randomization in one clock period. The method has the advantages that the dependency of the supposed power and practical power consumption track based on hamming weight in the AES algorithm can be effectively reduced; the power analysis attack based on the hamming weight module can be effectively resisted.

Description

technical field [0001] The invention relates to the technical field of integrated circuit hardware implementation and information security, in particular to a random delay-based AES algorithm-oriented anti-power consumption attack method. Background technique [0002] With the rapid development of Internet technology and information technology, information encryption technology has very important applications in many fields. Cryptographic products can be realized by software or hardware, but hardware-based cryptographic devices have become a research hotspot due to the advantages of faster speed and lower power consumption than software. Various encryption chips based on algorithms such as DES (Data Encryption Standard, Data Encryption Standard) and AES (Advanced Encryption Standard, Advanced Encryption Standard) have been extensively researched and developed. [0003] Cryptographic chips are also facing various security risks. In recent years, side-channel attacks represen...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L9/00H04L9/06
CPCH04L9/003H04L9/0631
Inventor 曹鹏申艾麟陈圣华陆启乐刘波杨锦江
Owner SOUTHEAST UNIV
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