AES-algorithm-oriented power analysis attack resistant method based on random time delay
A random delay and anti-power consumption technology, applied in countermeasures against encryption mechanisms, encryption devices with shift registers/memory, digital transmission systems, etc., can solve the problems of high implementation costs, high impact on performance and hardware resource overhead, To solve problems such as cumbersome solutions, achieve good anti-attack effect, low anti-attack cost, and good compatibility
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[0021] The technical solution of the present invention will be further introduced below in combination with specific embodiments.
[0022] The traditional AES algorithm consists of 3 parts, which are the initial key addition, 9 rounds of the same round operation, and the 10th round of final transformation. Each round requires a round key to complete the key addition operation, and there are eleven subkeys in total, denoted as Kn (n=0,...,10). The subkey is obtained by expanding the initial key. The 9-cycle round operation in the middle of the AES algorithm includes four operations: byte replacement, row shift, column mixing, and key addition. The transformation at the end of the tenth round includes three operations: byte replacement, row shift and key addition. AES will generate an intermediate value data at the end of each round, which can be recorded as Dn (n=0,...,10) and stored in the register, where D10 is the ciphertext output.
[0023] Such as figure 1 As shown, ta...
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