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Improvement method for dislocation defect in embedded SiGe epitaxy

An embedded silicon germanium and epitaxy technology, applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as dislocation defects in silicon germanium epitaxy, and achieve the effects of ensuring germanium concentration, improving electrical properties, and increasing stress

Inactive Publication Date: 2016-06-15
SHANGHAI HUALI MICROELECTRONICS CORP
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Problems solved by technology

In the process of using the existing silicon germanium selective epitaxy, using transmission electron microscope scanning, it is found that 100% of the silicon germanium epitaxy has dislocation defects

Method used

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  • Improvement method for dislocation defect in embedded SiGe epitaxy
  • Improvement method for dislocation defect in embedded SiGe epitaxy
  • Improvement method for dislocation defect in embedded SiGe epitaxy

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Embodiment Construction

[0025] The present invention will be further described below in conjunction with specific embodiment and accompanying drawing, set forth more details in the following description so as to fully understand the present invention, but the present invention can obviously be implemented in many other ways different from this description, Those skilled in the art can make similar promotions and deductions based on actual application situations without violating the connotation of the present invention, so the content of this specific embodiment should not limit the protection scope of the present invention.

[0026] First, the inventors of the present case realized that in the embedded SiGe selective epitaxy process, there is a certain relationship between the germanium concentration and the thickness of the SiGe film. image 3 It is a schematic diagram of the Matthews-Blakeslee theoretical curve based on the silicon-germanium thin film in the method for improving dislocation defects...

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Abstract

The invention provides an improvement method for a dislocation defect in embedded SiGe epitaxy. The improvement method comprises the following steps of firstly, appropriately reducing germanium concentration within a certain growth thickness range of a SiGe thin film during the reaction process of the SiGe epitaxy; secondly, gradually increasing the germanium concentration, and forming a linear concentration gradient until the average germanium concentration is exceeded; and finally, maintaining constant germanium concentration so as to complete growth. Compared with the prior art, the dislocation defect of the SiGe thin film induced by lattice mismatching caused by direct change of the germanium concentration during the growth process of the embedded SiGe epitaxy is reduced, the SiGe stress is improved, and the electrical property of a P-channel metal oxide semiconductor (PMOS) transistor is improved.

Description

technical field [0001] The invention relates to the technical field of preparation of embedded silicon germanium epitaxy, in particular, the invention relates to a method for improving dislocation defects of embedded silicon germanium epitaxy. Background technique [0002] It is well known that the performance of CMOS circuits is largely constrained by PMOS transistors. Therefore, any technology that can improve the performance of PMOS to the level of NMOS is considered beneficial. In 90nm PMOS, Intel engineers etched and removed the source and drain of the device, and then redeposited a silicon germanium (SiGe) layer, so that the source and drain would generate a compressive stress on the channel, thereby improving the PMOS performance. transfer characteristics. [0003] figure 1 It is a PMOS structure of germanium-silicon source / drain implantation-induced strain technology in the prior art. Such as figure 1 As shown, silicon germanium source / drain implantation-induced...

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Application Information

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IPC IPC(8): H01L21/02H01L21/20
Inventor 谭俊周海锋康俊龙
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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