Chip sealing ring structure and manufacturing method thereof

A manufacturing method and sealing ring technology, which are used in the manufacture of semiconductor/solid-state devices, electrical components, and electrical solid-state devices, etc., can solve the problems of complex structure and low rupture strength, and achieve simple structure, improved yield, and enhanced resistance to The effect of burst strength

Active Publication Date: 2016-03-02
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a chip sealing ring structure and its manufacturing method, which are used to solve the problems of low crack resistance or too complicated structure of the chip sealing ring structure in the prior art

Method used

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  • Chip sealing ring structure and manufacturing method thereof
  • Chip sealing ring structure and manufacturing method thereof
  • Chip sealing ring structure and manufacturing method thereof

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Embodiment 1

[0044] like image 3 and Figure 4 ~ Figure 7 As shown, the present embodiment provides a method for manufacturing a chip sealing ring structure, including steps:

[0045] like image 3 and Figure 4 As shown, step 1) S11 is first performed to form an annular dielectric layer 10 surrounding the chip 20 on the peripheral side of the chip 20 .

[0046] As an example, the material of the annular dielectric layer 10 is silicon dioxide, of course, other dielectric materials such as silicon nitride are also applicable, and are not limited thereto.

[0047] In addition, the shape of the annular dielectric layer 10 depends on the shape of the chip 20. In this embodiment, the shape of the chip 20 is rectangular, and the annular dielectric layer 10 has a rectangular ring structure.

[0048] As an example, the annular dielectric layer 10 can be prepared by chemical vapor deposition and other methods, such as plasma enhanced chemical vapor deposition and the like. In this embodiment,...

Embodiment 2

[0074] Such as image 3 and Figure 8 As shown, this embodiment provides a method for manufacturing a chip sealing ring structure, the basic steps of which are as in Embodiment 1, wherein the plurality of dielectric columnar structures 103 between the inner dielectric ring 101 and the outer dielectric ring 102 are in double rows distributed.

[0075] Such as Figure 8 As shown, this embodiment also provides a chip sealing ring structure, the basic structure of which is the same as that of Embodiment 1, wherein a plurality of dielectric columnar structures 103 between the inner dielectric ring 101 and the outer dielectric ring 102 are distributed in double rows.

Embodiment 3

[0077] Such as image 3 and Figure 9 As shown, this embodiment provides a method for manufacturing a chip sealing ring structure, the basic steps of which are as in Embodiment 1, wherein the plurality of dielectric columnar structures 103 between the inner dielectric ring 101 and the outer dielectric ring 102 are in multiple rows distributed.

[0078] Such as Figure 9 As shown, this embodiment also provides a chip sealing ring structure, the basic structure of which is the same as in Embodiment 1, wherein the plurality of dielectric columnar structures 103 between the inner dielectric ring 101 and the outer dielectric ring 102 are distributed in multiple rows.

[0079] As mentioned above, the present invention provides a chip sealing ring structure and a manufacturing method thereof, the manufacturing method comprising the steps of: 1) forming an annular dielectric layer 10 surrounding the chip on the peripheral side of the chip; 2) removing the annular dielectric layer P...

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Abstract

The invention provides a chip sealing ring structure and a manufacturing method thereof. The manufacturing method comprises the following steps of 1) forming an annular dielectric layer surrounding the chip at a peripheral side of the chip; 2) removing parts of dielectric materials of a central area of the annular dielectric layer and forming an inner dielectric ring, an outer dielectric ring and a plurality of dielectric cylindrical structures located between the inner dielectric ring and the outer dielectric ring; 3) filling a metal material in a blank area between the inner dielectric ring and the outer dielectric ring; 4) removing the metal material of an annular dielectric layer surface till that the annular dielectric layer is exposed. Through manufacturing the plurality of dielectric cylindrical structures and a metal material filling layer in the chip sealing ring structure, the fracture resistance intensity of a chip sealing ring is greatly reinforced so that damages in a chip, which are caused by a stress failure, are avoided during a chip cutting process and other processes and a yield rate of the chip is increased. The structure is simple, and the structure and the method are suitable for industrial production.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a chip sealing ring structure and a manufacturing method thereof. Background technique [0002] Integrated circuits are usually fabricated on silicon wafers or other semiconductor material substrates, then packaged and tested. When packaging, the integrated circuit must first be sawed. The mechanical force of cutting can cause tiny cracks to form on the edges, especially near the corners. The formed cracks may advance toward the central circuit area of ​​the integrated circuit and cause damage to the circuit area therein. In order to protect the circuit area at the center of the integrated circuit, a chip sealing ring (seal ring) is generally arranged on the integrated circuit chip between the circuit area and the dicing line. The chip sealing ring can prevent any cracks from invading the circuit area inside the integrated circuit, for example, cracks caused by stres...

Claims

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Application Information

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IPC IPC(8): H01L23/31H01L21/56
Inventor 张贺丰
Owner SEMICON MFG INT (SHANGHAI) CORP
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