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Formation method of semiconductor device

A semiconductor and device technology, applied in the field of semiconductor device formation, can solve problems such as unstable performance and poor transistor morphology, and achieve the effects of stable performance, prevention of leakage current, and good electrical isolation.

Active Publication Date: 2015-11-25
SEMICON MFG INT (SHANGHAI) CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, the transistors with the stress layer formed by the prior art have poor morphology and unstable performance

Method used

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  • Formation method of semiconductor device
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  • Formation method of semiconductor device

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Embodiment Construction

[0031] As described in the background, the transistors with stress layers formed in the prior art have poor morphology and unstable performance.

[0032] Please refer to figure 1 , figure 1 It is a schematic cross-sectional structure diagram of a transistor with a stress layer according to an embodiment of the present invention, including: a substrate 100, the substrate 100 has a first region 101 and a second region 102, between the first region 101 and the second region 102 The substrate 100 in between has a shallow trench isolation structure 103 ; a gate structure 104 on the surface of the substrate 100 ; and a stress layer 105 in the substrate 100 on both sides of the gate structure 104 .

[0033]Wherein, the forming method of the stress layer 105 includes: forming openings in the substrate 100 on both sides of the gate structure 104 by etching; and forming the stress layer 105 in the openings by using a selective epitaxial deposition process. However, since the STI struc...

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Abstract

Semiconductor devices and fabrication methods are provided. A semiconductor substrate is provided having dummy gate structures formed thereon. A stress layer is formed in the semiconductor substrate between adjacent dummy gate structures. A first dielectric layer is formed on the semiconductor substrate, the stress layers, and the sidewall spacers of the dummy gate structures, exposing dummy gate electrode layers. Gate structures are formed in the dielectric layer to replace the dummy gate structures. The gate structures include functional gate structures and at least one non-functional gate structure. The at least one non-functional gate structure is removed to form at least one second opening in the first dielectric layer. At least one third opening is formed in the semiconductor substrate at a bottom of the at least one second opening. A second dielectric layer is formed in the at least one second opening and the at least one third opening.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor device. Background technique [0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration. Transistors are currently being widely used as the most basic semiconductor devices, so as the element density and integration of semiconductor devices increase, the gate size of transistors has become shorter than before. However, the shortening of the gate size of the transistor will cause the short-channel effect of the transistor, thereby generating leakage current, and ultimately affecting the electrical performance of the semiconductor device. At present, the prior art mainly improves the performance of semiconductor devices by increasing carrier mobility. When the mobility of carriers is increased, the driving curren...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L21/28
CPCH01L29/161H01L21/02532H01L21/0262H01L21/02636H01L21/306H01L21/3065H01L21/308H01L21/3105H01L21/321H01L21/762H01L21/8234H01L27/088H01L29/16H01L29/66H01L29/78H01L21/28123H01L21/30617H01L21/76224H01L21/823437H01L21/823481H01L29/165H01L29/66545H01L29/7848H01L21/30604H01L21/31053H01L21/32115H01L29/1608
Inventor 洪中山
Owner SEMICON MFG INT (SHANGHAI) CORP
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