Capacitance mismatch calibration circuit and calibration method applied to single-ended sar ADC

Abstract

The invention discloses a single-end SAR ADC capacitance mismatch calibration method, which can calibrate the error caused by the capacitance mismatch of the SAR ADC. This method only needs to insert two pairs of redundant capacitors in the analog domain, and compensates for capacitance mismatch in the digital domain. The binary capacitor DAC containing two pairs of redundant point capacitors includes the segmented binary capacitor DAC and the redundant capacitors Cjr+, Cjr- inserted in the lowest bit Cj of the segmented capacitor MSB segment, and the redundant capacitors Cqr+, Cqr+ inserted in the LSB segment Cqr‑. The redundant bit calculation module adds the inserted redundant bit and other normal bits to calculate an effective output of N-bit. The capacitance mismatch calibration module performs capacitance mismatch compensation on the output result. This calibration method only adds two pairs of redundant capacitors to the traditional SAR ADC structure, and the calculation of mismatch compensation is performed in the digital domain, thereby reducing the layout area and the complexity of the analog circuit.

Description

technical field [0001] The invention relates to a mismatch calibration method applied to a single-end SAR ADC capacitance, which belongs to the SAR ADC calibration technology. Background technique [0002] High-precision SAR ADC (Successive Approximation Register-type Analog-to-Digital Converter) needs to use larger capacitors to meet the requirements of capacitor matching due to the limitation of its capacitor mismatch, especially when the accuracy is higher than 12-bit. Capacitor mismatch calibration is required to address the effects of capacitor mismatch. However, with large DAC (digital-to-analog converter) capacitors, settling time is thus limited and power consumption increases. In addition, the traditional calibration method requires a separate calibration DAC array for each capacitor that needs to be calibrated. Although the calibration DAC array only needs about 5 bits, once there are many capacitors that need to be calibrated, the capacitance of the calibration D...

AI Technical Summary

Problems solved by technology

However, with large DAC (digital-to-analog converter) capacitors, settling time is limited and power consumption increases

In addition, the traditional calibration method requires a separate calibration DAC array for each capacitor that needs to be calibrated. Although the calibration DAC array only needs about 5 bits, once there are many capacitors that need to be calibrated, the capacitance of the calibration DAC array may be different from that of the DAC itself. The area occupied by the array is equivalent, which directly leads to the increase of chip cost

[0003] Although the non-binary capacitance DAC arrays in recent years can realize capacitance mismatch calibration, due to the use of non-binary capacitance DAC arrays, the matching degree of its layout will be significantly worse than that of binary capacitance DAC arrays, and in digital logic, due to the need to store each The weight of each capacitor, its complexity is also increased a lot

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