Chip and forming method, packaged product, method for improving yield rate of packaged product

Abstract

A chip and its forming method, packaging finished products, and a method for improving the yield rate of packaged finished products. The chip forming method includes: providing a chip pattern, the chip pattern including a plurality of interconnected metal layer patterns, and recording interconnected metal layers with a metal density less than 0.3; Chip pattern forming a chip, including forming an interconnection metal layer according to the interconnection metal layer pattern, when forming an interconnection metal layer with a metal density less than 0.3, forming a filling metal in the gap between the interconnection metal lines of the interconnection metal layer line, so that the sum of the metal density of the interconnection metal line and the filling metal line is greater than or equal to 0.3. During the packaging process, the metal density of the interconnected metal layer is greater than or equal to 0.3, and the interlayer dielectric material layer between two adjacent interconnected metal layers can withstand relatively large stress without causing a gap between the adjacent interconnected metal layers. The interlayer dielectric material layer and the plug layer in it are broken, the interconnection performance between two adjacent interconnection metal layers is good, and the package yield rate can meet the requirements of mass production.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a chip and a forming method, a packaged product, and a method for improving the yield rate of the packaged product. Background technique [0002] In the semiconductor chip packaging process, solder bumps are formed on the front of the chip, and then the chip is flipped over and connected to the packaging substrate, electrically and mechanically connected to the circuit. This packaging method is called flip chip packaging (flip chip) method . [0003] refer to figure 1 , the high-density IO chip of the existing semiconductor technology of 40nm / 28nm process generally adopts a flip-chip packaging method based on copper pillar bump (Copper Pillar Bump) 1 . A plurality of copper pillar bumps 1 distributed on the front surface of the chip 2 are soldered to bump pads (Bump Pads) 4 on the front surface of the substrate 3 respectively. Next, solder balls (Solder Ball) 5 are form...

AI Technical Summary

Problems solved by technology

In this way, the interconnection between two adjacent interconnected metal layers will be disconnected (Open), causing the chip to fail, for example, some functions of the chip cannot work normally or the performance of the chip cannot meet the design requirements, resulting in a high yield rate. reduce

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