Semiconductor package and lead rack

Abstract

A semiconductor package is disclosed, which includes: a die paddle portion; a plurality of conductive portions circumventing the die paddle portion; a power bus bar and a ground bus bar formed around the periphery of the die paddle portion; a semiconductor element attached to the die paddle portion and electrically connected to the conductive portions, the power bus bar, and the ground bus bar by a plurality of bonding wires; and an encapsulant encapsulating the semiconductor element and the bonding wires. The ground bus bar extends outward along the power bus bar and is mutually configured with the power bus bar so as to reduce the loop inductance and resistance of the power bus bar while in use.

Description

technical field [0001] The invention relates to a semiconductor package, in particular to a semiconductor package and a lead frame which include a lead frame and can reduce the inductance and resistance of its power strip. Background technique [0002] With the vigorous development of the electronics industry, many high-end electronic products are gradually developing towards light, thin, short, small and other high-density directions. The semiconductor packaging structure has also developed many different packaging modules, for example, square flat Package (quad flat package, QFP). At present, the quad flat package is used in large-scale or ultra-large-scale integrated circuits. The lead frame has a small pitch and thin pins, so multiple power lines, signal lines and ground lines can be provided. [0003] Traditional QFP cannot meet the application requirements of high-speed and high-frequency components, so if you need to apply high-speed and high-frequency components, yo...

AI Technical Summary

Problems solved by technology

[0007] But, in existing semiconductor package 1 ', although the quantity of this power bar 104 is less than Figure 1A' The number of power pins 102 shown, but the volume of the power strip 104 is greater than Figure 1A' The volume of the power pin 102 shown, and the volume of the ground pad 103' is greater than Figure 1A' The volume of the grounding pin 103 as shown makes it impossible to reduce the inductance and resistance of the power strip 104. Therefore, for high-speed electronic products, the voltage and resistance are not easy to reduce, so the electronic products still generate a lot of noise. thus affecting electrical performance

[0008] In addition, in the existing semiconductor package 1', the semiconductor chip 11, the power bar 104 and the ground pad 103' generate a long circuit return path, so the inductance effect of the QFP cannot be effectively reduced.

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