Tunneling field effect transistor and preparation method thereof

Abstract

Disclosed is a tunneling field effect transistor. The tunneling field effect transistor comprises a source region, two drain regions and two grid regions. The two drain regions are arranged on opposite two sides of the source region in a first direction; the two grid regions are arranged on opposite two sides of the source region; first extension layers and grid medium layers are arranged between the source region and the two grid regions, wherein the first extension layers are arranged between the source region and the grid medium layers and form tunneling junction with the source region; the two drain regions and the two grid regions are arranged around the source region, so that the source region can be completely under the control of the two grid regions, and current carrying electrons in the overlapped regions of the source region and the grid regions can tunnel under the action of the electric field of the grid regions; the first extension layers are arranged between the source region and the grid medium layers and is of a linear tunneling mode, thereby being large in tunneling area; the direction of the electric field of the grid regions and the tunneling direction of the electrons of the source region are on the same line, so that high tunneling probability can be achieved, and tunneling current can be increased. Besides, the invention also provides a preparation method of the tunneling field effect transistor.

Description

technical field [0001] The invention relates to a tunneling field effect transistor and a preparation method thereof. Background technique [0002] Since the birth of the first integrated circuit, integrated circuit technology has been developing along the track of "Moore's Theorem". At present, the size of semiconductor transistors has reached 28nm and 22nm, and the size of transistors will continue to decrease, requiring lower supply voltage and Threshold voltage, but the traditional MOS structure has reached the limit, and the generation of low threshold voltage is becoming more and more difficult. This is because the threshold voltage decreases, and the switching ratio (Ion / Ioff, where Ion is the on-state current, Ioff is the off-state current, the gate voltage is greater than the threshold voltage to obtain Ion, and the gate voltage is less than the threshold voltage to obtain Ioff) will also decrease. resulting in longer switching times. [0003] At the same time, be...

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Problems solved by technology

Therefore, in the prior art, the use of a point tunneling mechanism leads to a low probability of carrier tunneling, which makes TFETs have the disadvantage of low tunneling current.

At the same time, the overlapping area between the source region and the gate region is limited, so that the tunneling area is small, and the tunneling current density is proportional to the tunneling area and the tunneling probability, therefore, resulting in a lower tunneling current

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