Forming method of transistor

Abstract

The invention provides a forming method of a transistor. The method comprises the following steps that a substrate is provided, and a first semiconductor layer is formed on the substrate; a second semiconductor layer is formed on the first semiconductor layer; the partial second semiconductor layer and the partial first semiconductor layer are etched, and a plurality of semiconductor patterns in parallel distribution in the first direction are formed; first semiconductor patterns formed at the bottom of the second semiconductor patterns are removed, and a cavity is formed; an oxidation process is carried out, oxidation layers are formed on the side wall and the bottom of second semiconductor patterns and the surface of the substrate, and the oxidation layers fully fill the cavity; the partial second semiconductor patterns are etched, the second semiconductor patterns are cut in the second direction, and a plurality of second grooves parallelly distributed in the second direction are formed in the second semiconductor patterns; first grooves and the second grooves are fully filled with insulation layers, and the surfaces of the insulation layer are aligned with the surfaces of the semiconductor patterns; grid electrode structures are formed on the surfaces of the broken semiconductor patterns. The forming method has the advantage that the manufacturing cost is reduced.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a transistor. Background technique [0002] With the improvement of component density and integration of semiconductor devices, the gate size of transistors is getting smaller and smaller, and the smaller gate size of transistors will intensify the short channel effect, causing leakage current in transistors and affecting the electrical properties of semiconductor devices. performance. [0003] In order to overcome the short-channel effect of transistors and suppress leakage current, the prior art proposes a transistor device formed on an insulator, such as a fully-depleted semiconductor-on-insulator (FD-SOI, Fully-Depleted Semiconductor On Insulator) transistor, And Partly-Depleted Semiconductor On Insulator (PD-SOI, Partly-Depleted Semiconductor On Insulator) transistors. [0004] Figure 1 to Figure 2 It is a schematic cross-sectional structure...

AI Technical Summary

Problems solved by technology

[0008] At present, there are mainly three kinds of mature SOI substrate formation processes, specifically SIMOX (Separation by Implanted Oxygen) process, silicon wafer bonding process, and Smart Cut (Smart Cut) process. The cost is relatively high, especially as ultra-thin silicon-on-insulator (ETSOI, Extremely Thin SOI) substrates are used in integrated circuit manufacturing, the thickness uniformity of the top silicon layer has an important impact on the electrical performance of the device

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