Pipeline ADC (analog to digital converter) and error calibration method thereof

Abstract

The invention discloses a foreground digital calibration method applicable to a pipeline ADC (analog to digital converter). On the basis of the structure of the traditional pipeline ADC, a level-calibrated adding circuit is added on a level with the error required to be calibrated. During calibration period, four special inputs are supported for the level-calibrated adding circuit with an error level required to be calibrated and a sampling capacitor, and by the aid of the foreground digital calibration computing and calibrating circuit, a calibration level capacitor mismatch error, a operational amplifier mismatch error and a sub-DAC (digital to analog converter) reference voltage error are extracted. During the normal working period, the foreground digital calibration computing and calibrating circuit works. The foreground digital calibration method is simple in structure, few additional elements are added, sequential control is easy, few registers are required, and digital circuit design is low in difficulty and short in period. By the use of the foreground digital calibration method, static characteristics of the pipeline ADC is calibrated excellently, and a certain calibration effect of dynamic characteristics of the pipeline ADC is achieved.

Description

technical field [0001] The invention relates to an analog-to-digital converter used in an infrared focal plane array readout circuit, in particular to a pipelined analog-to-digital converter and an error calibration method thereof. [0002] Background technique [0003] The readout circuit (ROIC) is one of the key components of the uncooled infrared focal plane array (IRFPA). Its main function is to preprocess the weak signal induced by the infrared detector (such as integration, amplification, filtering, sampling / holding, etc.) ) and parallel / serial conversion of array signals. Depending on the material used and the working method of the detector, the structure of the readout circuit changes accordingly to obtain the maximum signal-to-noise ratio (SNR) while meeting the requirements of the frame rate. [0004] ROIC belongs to digital-analog hybrid integration technology. The pixel circuit part is an analog circuit, which has special requirements for the channel width-to-...

AI Technical Summary

Problems solved by technology

[0006] In the classic non-calibration pipelined ADC, capacitance mismatch error is unavoidable due to the manufacturing process, which to some extent limits the effective trade-off between resolution and sampling rate, especially in large arrays, In the readout technology of high frame rate uncooled infrared focal plane array, there are limitations of higher resolution and higher sampling rate

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