SoC (system on chip) dynamic voltage frequency scaling method with foresight

A dynamic voltage and frequency adjustment technology, applied in the direction of data processing power supply, etc., can solve the problems of inability to achieve performance and power consumption, limited prediction, and inability to make accurate responses, so as to reduce power consumption and ensure performance.

Inactive Publication Date: 2014-12-17
SOUTH CHINA UNIV OF TECH
View PDF4 Cites 19 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Regardless of whether DVFS is implemented by software or hardware, because it is necessary to collect system load and predict the load in the next period, this makes the voltage and frequency adjustment of the system have a delay, and the balance between performance and power consumption cannot be achieved.
[0

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • SoC (system on chip) dynamic voltage frequency scaling method with foresight
  • SoC (system on chip) dynamic voltage frequency scaling method with foresight

Examples

Experimental program
Comparison scheme
Effect test

Embodiment

[0031] see figure 1 As shown, the SoC system architecture diagram adopting the method of the present invention, the SoC chip includes: a touch screen controller, a power management unit (PMU, Power Management Unit), a clock management unit (CMU, Clock Management Unit), a DVFS module, and a simplified instruction set Processor (RISC CPU), on-chip bus (SoC BUS), graphics unit (Graphics Unit), memory controller (Memory Controller), input and output interface module (I / O Interface), etc.; and the above-mentioned SoC system level The controller, unit or module contained in the chip adopts the form of IP core and is described in Verilog hardware description language.

[0032] The above SoC chip also manages the power consumption of the SoC system-on-chip through an external power management integrated circuit PMIC.

[0033] The working process of the present invention is described in detail below, see figure 2 Shown:

[0034] 1. After the SoC using this method is powered on, the...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses a SoC (system on chip) dynamic voltage frequency scaling method with foresight and belongs to the field of chip design and application. The invention aims to solves the delay problem of dynamic voltage frequency scaling in a master control chip of a mobile device, realize the reduction of power consumption whiling guaranteeing the CPU (central processing unit) performance and improve the user experience. Compared with a traditional scaling method, the CPU dynamic voltage frequency scaling of a SoC is with foresight and is realized on the basis of the following principle: a capacitive screen controller is integrated to the SoC; the capacitive screen controller adopts the digital-analog mixed signal design, not only has the functions of digital-analog conversion, coordinate output and multipoint touch control of a traditional capacitive screen controller, but also has the functions of touch strength detection, touch frequency statistical and touch length statistical; then a DVFS (dynamic voltage frequency scaling) module outputs a CPU voltage and frequency with foresight through judgment according to the parameters and the load situation of the operating system, and the CPU voltage and frequency are also output to a power management unit and a clock management unit of the SoC for appropriate scaling.

Description

technical field [0001] The invention relates to a SoC chip power management technology, in particular to a SoC dynamic voltage frequency adjustment method with forward-looking properties. Background technique [0002] At present, with the development of mobile devices and the popularization of SoC chips (abbreviation of System on Chip, called system-on-chip), we urgently need to reduce the power consumption of SoC chips. Great progress has been made. In order to prolong battery life, power consumption must be reduced; on the other hand, reducing power consumption is conducive to reducing device heating, improving stability and user experience. At present, in order to reduce power consumption, more and more chips support the dynamic voltage and frequency adjustment technology DVFS (Dynamic Voltage and Frequency Scaling). This type of technology (patent: 200710039255.9) mainly contains two kinds of implementation methods: 1. Software-based DVFS implementation: generally colle...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): G06F1/32
Inventor 张义胡跃明陈安
Owner SOUTH CHINA UNIV OF TECH
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products