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Distributed parallel computing method and system for physical implementation of large scale integrated circuit

A large-scale integrated circuit and distributed computing technology, applied in computing, electrical digital data processing, special data processing applications, etc., to achieve fast design acceleration, minimize data update delay, and optimize management effects

Inactive Publication Date: 2014-09-10
领佰思自动化科技(上海)有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Due to the reduction of feature size, the number of transistors that can be accommodated on the chip increases accordingly, and the problem scale and complexity of circuit design also continue to increase, which makes traditional physical implementation tools must have the ability to deal with larger-scale and complex problems

Method used

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  • Distributed parallel computing method and system for physical implementation of large scale integrated circuit
  • Distributed parallel computing method and system for physical implementation of large scale integrated circuit
  • Distributed parallel computing method and system for physical implementation of large scale integrated circuit

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Embodiment Construction

[0043] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0044] In this implementation, a distributed parallel computing method for the physical realization of large-scale integrated circuits is designed. The overall problem of physical realization in different stages is divided into physical realization sub-problems in units, and then these sub-problems are expressed as sub-tasks. , Put it into the subtask queue pool, the subtask will be calculated and processed by the distributed computing server, and the result of the calculation will be sent back to the main process. See figure 1 As shown, the main program can perform parallel computing in different physical implementation stages. When parallel computing is started, the task division thread of the main program divides the overall problem into independent sub-problems according to different division methods, and adds them to the task queue. Poo...

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Abstract

The invention discloses a distributed parallel computing method and system for physical implementation of a large scale integrated circuit. According to the method, physical design problems of different stages are divided into sub-problems on a host, different division methods are applied to the different stages, then the sub-problems are sent to distributed servers by the host in a network communication mode to be computed, and computing results are sent back to the host. The host and a computing cluster are respectively provided with a servo management program, the program is an impotent component of a distributed computing frame and is in charge of management of distributed computing resources, and management of the distributed computing resources comprises resource allocation, resource recovery and the like. According to the distributed parallel computing method and system for physical implementation of the large scale integrated circuit, the physical design problems of a super-large scale integrated circuit can be solved rapidly and effectively, physical design efficiency of the integrated circuit can be improved greatly, and rapider and more-effective physical design of the large scale integrated circuit can be achieved compared with multithreading computing on a single computer.

Description

Technical field [0001] The invention belongs to the field of integrated circuit design, in particular to the technical category of integrated circuit design optimization under an integrated circuit manufacturing process with an interconnect line width of 65nm and below, and specifically relates to a distributed parallel computing that is physically realized by a large-scale integrated circuit Method and system. Background technique [0002] The integrated circuit is designed by the designer with the help of electronic design automation (EDA) tools to design the integrated circuit layout and deliver it to the integrated circuit manufacturer, through the circuit mask preparation (Mask) and the wafer (Wafer) for oxidation, doping, lithography, etc. A series of manufacturing processes transfer the circuit mask to the wafer to realize its circuit function. For digital circuit design, the layout design process includes steps such as behavior-level synthesis, logic synthesis, physical ...

Claims

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Application Information

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IPC IPC(8): G06F9/46G06F17/50
Inventor 陈刚李小南
Owner 领佰思自动化科技(上海)有限公司
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