A vacuum brazing chip mounting process method without load and low void ratio

Abstract

The invention relates to a low-voidage vacuum brazing chip mounting technique free of loads. The technique comprises the following steps that (1), a sputtering Au technology is adopted in the back face of a chip to be brazed, and the back face is metallized; (2), the chip to be brazed is arranged on a to-be-brazed gold plating chip mounting area of an integrated circuit packaging shell, and brazing materials are placed between the chip to be brazed and the to-be-brazed gold plating chip mounting area; (3), a test sample to be brazed is placed in brazing equipment to be brazed according to technological conditions specially designed. In the brazing process, temperature curve optimization is combined with vacuum degree control, the air pressure difference is used for replacing the pressing block loads, optimization design is carried out on the temperature interval, the heating rate, the heat preservation time and the vacuum degree, the optimal technological conditions are determined, the problem that the chip is damaged due to adopted loads in the traditional method is solved, the brazing voidage is lowered, and the brazing yield and brazing quality are obviously improved.

Description

technical field [0001] The invention belongs to the technical field of semiconductor ceramic packaging technology, and in particular relates to a vacuum brazing chip loading process method without load and low void ratio. Background technique [0002] At present, in integrated circuit packaging, the size of the chip mounted by soldering is usually less than 10mm×10mm. During the process of soldering the chip, it is necessary to use a load such as a pressure block to provide the downward force of the chip, so that the chip, the soldering piece and the shell substrate are in contact. It is more compact, which inevitably makes the contact between the pressing block and the chip surface, whether it is "point" contact or "surface" contact, which puts forward high requirements on the cleanliness of the chip surface. However, the tiny silicon powder and silicon slag on the chip surface will The chip is damaged under the action of the pressing block, and the surface of the pressing ...

AI Technical Summary

Problems solved by technology

[0002] At present, in integrated circuit packaging, the size of the chip mounted by soldering is usually less than 10mm×10mm. During the process of soldering the chip, it is necessary to use a load such as a pressure block to provide the downward force of the chip, so that the chip, the soldering piece and the shell substrate are in contact. It is more compact, which inevitably makes the contact between the pressing block and the chip surface, whether it is "point" contact or "surface" contact, which puts forward high requirements on the cleanliness of the chip surface. However, the tiny silicon powder and silicon slag on the chip surface will The chip is damaged under the action of the pressing block, and the surface of the pressing block is easy to be stained after repeated use, and it will cause a large void rate inside the chip, which seriously affects the yield of the brazing chip, and the requirements for the chip are too harsh. As a result, some chips that are extremely prone to damage cannot be soldered and mounted

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