Semiconductor device manufacturing method

Abstract

The invention provides a manufacturing method for a stress semiconductor device. In the method, firstly a tensile stress layer is deposited on an NMOS area so as to deposit a compressive stress layer on a PMOS area, and then a compressive stress protective layer is deposited comprehensively; through a first CMP process, dummy gates are opened and because the compressive stress protective layer of a part thickness is kept on the tensile stress layer and on the compressive stress layer and the corrosion rate of the compressive stress protective layers in a wet-process corrosive liquid is significantly low, the tensile stress layer and the compressive stress layer are protected by the compressive stress protective layers on the tensile stress layer and the compressive stress layer and free from damages when dummy-gate insulating layers are corroded and thus defects in the prior art are overcome; and next, after grid grooves are formed, a second CMP process can be performed selectively so as to remove the remaining compressive stress protective layers and then manufacturing of a high-K grid insulating layer and a metal gate is completed and integration of a gate last and a dual stressliner is realized.

Description

technical field [0001] The invention relates to the field of manufacturing methods of semiconductor devices, in particular to an integration method of a double strain stress layer applied in a CMOS gate-last process. Background technique [0002] After semiconductor integrated circuit technology enters the technology node of 90nm feature size, it becomes more and more challenging to maintain or improve transistor performance. After the 90nm node, stress technology is gradually adopted to improve device performance. At the same time, in terms of manufacturing process, the high-K metal gate technology in the gate last process (gate last) is also gradually adopted to meet the challenges brought about by the continuous reduction of devices. In the stress technology, the dual stress layer (DSL, dual stressliner) technology has high compatibility with conventional processes and low cost, so it is adopted by major semiconductor manufacturers. [0003] DSL technology refers to the...

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Problems solved by technology

In this case DSL integration failed due to stress layer loss

In addition, for the case where TEOS is deposited on the device, although the TEOS covering the stress layer after CMP will protect the stress layer from corrosion, the corrosion rate of TEOS in DHF is also relatively high, and the process of removing the dummy gate insulating layer During the process, TEOS is in danger of being completely corroded by DHF, which will expose the underlying tensile stress silicon nitride to the environment of DHF, resulting in the corrosion of tensile stress silicon nitride

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