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Semiconductor device manufacturing method

A device manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of DSL integration failure, stress layer loss, etc.

Active Publication Date: 2017-11-03
SOI MICRO CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this case DSL integration failed due to stress layer loss

Method used

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  • Semiconductor device manufacturing method
  • Semiconductor device manufacturing method
  • Semiconductor device manufacturing method

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Embodiment Construction

[0028] Hereinafter, the present invention is described by means of specific embodiments shown in the drawings. It should be understood, however, that these descriptions are exemplary only and are not intended to limit the scope of the present invention. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present invention.

[0029] The present invention provides a method for manufacturing a semiconductor device, and in particular relates to a method for manufacturing a transistor using spacer technology. Please refer to the attached Figure 4-9 , the semiconductor device manufacturing method provided by the present invention will be described in detail.

[0030] First, see attached Figure 4 , on the semiconductor substrate 1 , NMOS 2 and PMOS 3 are formed, and different MOS transistors are isolated by STI structures 4 . Wherein, in this embodiment, a single crystal silicon ...

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Abstract

The invention provides a stress semiconductor manufacturing method. The method provided by the invention comprises the steps that a tensile stress layer is formed in an NMOS region; a compressive stress layer is completely formed; through photolithography and etching processes, the compressive stress layer of a certain thickness is retained on the tensile stress layer; and through a CMP process of the first time, a dummy gate is opened. The compressive stress layer of a certain thickness is retained on the tensile stress layer, and the corrosion rate of the tensile stress layer in wet corrosion liquid layer is very small, thus the tensile stress layer is protected by the compressive stress layer on the tensile stress layer and is not damaged when an insulating layer of the dummy gate is corroded. The defects of the prior art are overcome. After a gate groove is formed, the manufacturing of the high K gate insulating layer and the metal gate are finished. The integration of a post-gate process and a dual strain stress layer process is realized.

Description

technical field [0001] The invention relates to the field of manufacturing methods of semiconductor devices, in particular to an integration method of a double strain stress layer applied in a CMOS gate-last process. Background technique [0002] After semiconductor integrated circuit technology enters the technology node of 90nm feature size, it becomes more and more challenging to maintain or improve transistor performance. After the 90nm node, stress technology is gradually adopted to improve device performance. At the same time, in terms of manufacturing process, the high-K metal gate technology in the gate last process (gate last) is also gradually adopted to meet the challenges brought about by the continuous reduction of devices. In the stress technology, the dual stress layer (DSL, dual stress liner) technology has high compatibility with conventional processes and low cost, so it is adopted by major semiconductor manufacturers. [0003] DSL technology refers to th...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8238
CPCH01L21/823828
Inventor 秦长亮殷华湘尹海洲
Owner SOI MICRO CO LTD
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