Manufacturing method for semiconductor device

Abstract

The invention discloses a manufacturing method for a semiconductor device, for improving the mask of a side wall. The method comprises: forming a barrier layer and a sacrificial layer; by use of a CMP process, grinding the portions with quite big differences, of the left side and the right side of the upper portion of the side wall, leaving an approximately rectangular-shaped portion at the bottom of the side wall, and performing a subsequent side wall mask process by taking the approximately rectangular-shaped portion as a mask layer such that adverse consequences caused to subsequent etching by asymmetrical morphology of the side wall can be reduced as much as possible; and forming a second side wall by taking a first side wall formed by the previous side wall mask process as a dummy gate and executing a second CMP process to obtain a second side wall mask layer with good morphology so as to finish a second side wall mask process, i.e., QSPT.

Description

technical field [0001] The invention relates to the field of semiconductor device manufacturing methods, in particular to a transistor manufacturing method using a sacrificial layer and a barrier layer to improve sidewall transfer technology. Background technique [0002] After semiconductor integrated circuit technology enters the technology node of 90nm feature size, it becomes more and more challenging to maintain or improve transistor performance. In order to continue Moore's Law, the feature size of the device is required to be continuously reduced, but conventional 193nm lithography has basically reached its limit, and other technologies such as EUV and electron beam are still a long time away from commercial application. [0003] As a low-cost and easy-to-apply photolithography technology, spacer patterning technology (SPT) is considered to be able to be adopted in the next generation of feature sizes. And, in order to generate more lines at the same time, QSPT (quad...

AI Technical Summary

Problems solved by technology

[0004] However, sidewall transfer technology and QSPT technology also have obvious shortcomings: the left and right sides of the sidewall morphology are asymmetrical, resulting in different shapes formed by subsequent etching.

Since the shape of the first side wall itself is already irregular, after QSPT, the shape of the second side wall will be even worse, see the attached Figure 5 , wherein the two side profiles of the second side wall 14 are very unsatisfactory

This will seriously affect the morphology of the subsequent etching of the target

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