A Realization Method of 1588 Clock Synchronization Function

Abstract

The invention discloses a system and method for achieving a 1588 clock synchronization function. The high-precision clock synchronization function is achieved based on the P4080CPU of the Freescale corporation and the ACS9521 clock synchronization chip of the Semtech corporation. According to the scheme, due to the fact that the system and method are limited by the fact that a PHY and a MAC layer cannot print a timestamp through hardware, the mode of printing the timestamp on the ACS9521 through the hardware is adopted to reduce the error of calculated synchronization time to the greatest extent and to ensure synchronization precision, and meanwhile at the section from the PHY to the ACS9521, the hardware (PCD, port forwarding messages and FPGA modification messages ) is used for completing all the functions to avoid time errors caused by software participation to the greatest extent. The system and method can meet the synchronization needs of various communication devices, and dependency on a GPS and other satellite synchronization modes is avoided.

Description

technical field [0001] The present invention relates to a method for realizing the clock synchronization function, in particular to a 1588 clock synchronization function [0002] Systems and methods can be implemented. Background technique [0003] Currently in distributed networks, commonly used clock synchronization technologies include satellite reception such as GPS or Beidou and NTP [0004] etc., but the installation and maintenance of GPS and Beidou are difficult and costly, and the accuracy of NTP cannot meet the synchronization performance requirements of base station equipment (NTP is at the ms level). In order to solve the above problems, the industry is actively promoting the development and application of the 1588 protocol. 1588 has the advantages of ns-level accuracy, short information, less bandwidth resources, low overall cost, and high reliability. [0005] At present, the optional 1588 clock synchronization function solutions are as follows: [0006] 1)...

AI Technical Summary

Problems solved by technology

[0089] 5) Because the current FPGA needs to undertake many functions, the available resources are limited and cannot meet the resources required to realize the complex functions of the algorithm. At the same time, it is also limited by the main frequency, and there are problems with large traffic packets (Negative Solution 4)

[0090] 6) Time stamping should be closer to the bottom layer, the better, the closer to the bottom layer, the smaller the calculated time error, but the currently selected PHY has a bug in the support for time stamping (negates solution 3), and the P4080 time stamping is not It can only support TWO-STEP mode, not ONE-STEP mode (negates solution 2), so it can only be timestamped on ACS9521

The time consumption from PHY to ACS9521 will cause errors, so the operation of this section should be implemented by hardware as much as possible. Hardware implementation can ensure that the delay is a relatively fixed value, so that ACS9521 can compensate, instead of using software implementation. The time delay of the software is not fixed, which will cause inaccurate compensation

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