Side-channel attack resisting processor architecture based on random instruction delay

Abstract

The invention discloses a side-channel attack resisting processor architecture based on random instruction delay. The architecture is that an instruction memory is connected with an instruction random scheduling module, a central processing unit is connected with a multi-channel selector, a random flowing water section delay module and a data memory respectively, the multi-channel selector is connected with the instruction random scheduling module and a random waste instruction injection module respectively, and a random number generating module is connected with the random waste instruction injection module, the instruction random scheduling module and the random flowing water section delay module respectively. The side-channel attack resisting processor architecture enables a specific operation execution time point of side-channel attack not to be confirmed through an instruction random scheduling and out-of-order execution mode, a random waste instruction injection mode, a random flowing water section operation delay mode and the like, accordingly enables statistic analysis to be difficult to perform, greatly enhances the side-channel attack resisting capacity of a system and avoids cryptographic algorithm decryption caused by leakage of side-channel information.

Description

technical field [0001] The invention relates to the field of information security, and relates to a processor architecture against bypass attacks, in particular to a processor architecture against bypass attacks based on random instruction delay. Background technique [0002] Information security chips have been widely used in various fields, mainly to complete the safe storage of user key data, data encryption and decryption, digital signature and authentication, and identity authentication. The security chip is often used as the core of security control and the root of trust in various application systems, so the security of the security chip itself plays a key role in the entire system. [0003] The security of a security chip largely depends on the complexity of the cryptographic algorithm in the chip and the security of the key. Currently widely used cryptographic algorithms have reached a very high complexity, and cryptanalysis in the mathematical sense is almost impo...

AI Technical Summary

Problems solved by technology

However, a single random delay approach proved to be limited

Studies have shown that for DPA (Differential Power Analysis) attacks, after inserting random time delays, although a single bias spike is dispersed into several small spikes at different positions, which significantly reduces the signal-to-noise ratio of DPA attacks, but if the attacker can estimate the time The range of delays that may occur, that is, to determine the time delay window, then by analyzing the total power consumption in this time window, the signal-to-noise ratio of DPA attacks can be effectively improved, making the random delay technology invalid

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