Method for reducing v-groove on top of polysilicon in trench of trench-type power transistor

Abstract

The invention discloses a method of reducing a V-shaped groove at the top end of polycrystalline silicon inside a groove of a groove-type power transistor. The method comprises a first step of forming the groove on the power transistor, depositing the polycrystalline silicon inside the groove to form a grid and form the V-shaped groove at the top end of the polycrystalline silicon at the same time, depositing the polycrystalline silicon used for filling the V-shaped groove on the upper surface of the grid, and the etched and deposited polycrystalline silicon forming the V-shaped groove with a small depth. The method can greatly reduce the depth of the V-shaped groove at the top end of the polycrystalline silicon, reduce contactor (Cont) resistance on the grid, and prevent a switch component from losing effectiveness because the Cont resistance can not be connected with the grid. The method can be widely applied to forming of the grid inside the groove of the groove-type power transistor.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for reducing the V-shaped groove at the top of polysilicon in the trench of a trench-type power transistor. Background technique [0002] At present, power transistors are widely used in high-power switching devices, and such devices generally adopt a vertical conductive structure. In terms of the physical structure of the device, the trench structure is one of the typical structures, and it is widely used. [0003] The gate of the trench power transistor is located in the trench, and when forming the gate, it is necessary to fill the trench with polysilicon. In conventional processes, polysilicon is deposited to a thickness of approximately 6K. Because the trench is very deep (depth > 1.0 um), after the polysilicon fills the trench, the height of the top surface of the polysilicon in the trench in the horizontal direction is lower than that of the source. A...

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Problems solved by technology

This V-shaped groove will affect the leakage current of the switching device and increase the resistance of the Cont (contactor) above the gate, thereby affecting the switching speed and power consumption of the switching device. At the same time, the thickness of the ILD (internal dielectric layer) above the gate will increase with the As the depression of the V-shaped groove increases, this situation will narrow the Cont etching process window. When the depression reaches a certain level, it is more likely that the thickness of the ILD will be too thick to be etched cleanly, so that the Cont cannot be well connected to the gate, resulting in Switching device failure

[0004] At present, there are two improved processes that can solve the above problems: the first is to increase the thickness of polysilicon deposition (about 10K), but this process is not effective while increasing the cost; the second is to add a step before polysilicon etching Polysilicon CMP (Chemical Mechanical Polishing, chemical mechanical polishing) process, this process makes the polysilicon in the trench and the polysilicon above the source almost at the same level, and can significantly improve the V-shaped groove during etching, but the cost of polysilicon CMP is relatively high

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