Phase-locked loop and circuit and method of closed loop frequency self-calibration of phase-locked loop

Abstract

A phase-locked loop comprises a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, a frequency divider, a sigma-delta modulator and a closed loop frequency calibration circuit; the voltage-controlled oscillator at least comprises a capacitor array and an oscillator; and a reference clock signal coming from a crystal oscillator is input into the phase frequency detector and a processor, the phase frequency detector is connected with the oscillator successively through the charge pump and the loop filter, and the oscillator is connected with the phase frequency detector and the sigma-delta modulator through the frequency divider. The phase-locked loop can greatly shorten calibration time and improve calibration efficiency. The invention further relates to a circuit and a method of closed loop frequency self-calibration.

Description

[0001] technical field [0002] The invention relates to a phase-locked loop, its closed-loop frequency automatic calibration circuit and method. [0003] Background technique [0004] The phase-locked loop circuit is a feedback control circuit, which is characterized by using the input reference clock provided by the external crystal oscillator to control the frequency and phase of the internal oscillation signal of the loop, so as to obtain the required frequency signal. Phase-locked loops are widely used in wireless communication, navigation, control, instrumentation and other fields. Typical PLL circuits such as figure 1 As shown, it consists of a frequency detector 11, a charge pump 12, a loop filter 13, a voltage controlled oscillator 14 and a frequency divider 15. To realize a phase-locked loop circuit with fractional frequency division, it is necessary to add a sigma -delta modulator 16 to achieve a fractional divider ratio. In addition, in modern wireless commun...

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Problems solved by technology

Although this method is widely used, it has obvious disadvantages. Every time the frequency is adjusted, the loop needs to be broken, which increases the capture time; when comparing two signals, two counters are required, and due to the voltage-controlled oscillation The frequency difference between the adjacent tuning curves of the counter is small, so it takes a long counting cycle to be able to distinguish the required frequency difference, which means that the number of bits of the two counters must be sufficient, which increases additional power consumption and area

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