Data receiving and processing system of analog front end

Abstract

A data receiving and processing system of an analog front end is used for collecting asynchronous data at one or a plurality of analog front-end chips, converting data serial-parallel, synchronously processing the data, processing data format and the like. The data receiving and processing system mainly comprises a signal receiving and processing module, a data shifting and serial-parallel processing module, and an FIFO (first in first out) data synchronous processing module. The signal receiving and processing module is used for completely converting type of an input signal from a differential form to a single-ended form. The data shifting and serial-parallel processing module is used for completing asynchronous data collection for the analog front end chip and performing serial-parallel conversion. The FIFO data synchronous processing module is used for realizing different clock domains of a data write-in signal and a data read-out signal, reading master clocks of the data and a system to realize synchronous design output, and outputting different numerical values to odd and even data identification flags to be odd and even identifying data. The data receiving and processing system of the analog front end is high in data transmission rate, high in anti-jamming capability of data transmission, and high in reliability in data processing.

Description

technical field [0001] The invention relates to a data processing system. Background technique [0002] At present, the working space orbit height of aerospace remote sensing cameras is relatively high, and the service life is long. The analog-to-digital conversion device or analog front-end (AFE) device data output of the corresponding aerospace remote sensing camera signal processing circuit adopts single-line transmission mode, and the digital quantized data is output in parallel. There are many connections for data transmission, the transmission reliability is low, and the number of devices that need to be used to receive data or the number of FPGA chip pins used to receive data is large. [0003] In addition, the anti-radiation parameters used by some devices are not high enough, and the overall anti-radiation considerations of the circuit design are not comprehensive. The service life does not meet the requirements of high orbit and long service life of more than 5 ye...

AI Technical Summary

Problems solved by technology

[0005] In the existing signal processing circuit data receiving and processing system, because the output data of the analog-to-digital conversion AFE chip is parallel data, it needs to occupy a large number of points for data transmission, and the space size of a single circuit board and the pins of the FPGA chip used together The number is fixed, so the amount of data that can be processed by each circuit board will be limited; and because the analog-to-digital conversion AFE chip outputs a large number of parallel data bits and a high frequency, the data lines are prone to crosstalk and other interference, resulting in Bit errors occur in data transmission, and timing phase reception errors occur

In terms of software program, the existing signal processing data acquisition system needs to adjust the clock delay internally to collect the data, and the clock delay time needs to be adjusted in combination with the batch, grade and PCB circuit board condition of the actual chip, which will Takes more debugging time

Images