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Semiconductor device and method of manufacturing the same

A semiconductor, conductive type technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, transistors, etc., can solve problems such as hFE being smaller than expected value, inability to obtain V-NPN transistor characteristics, etc., to achieve the effect of reasonable manufacturing process

Inactive Publication Date: 2012-11-28
SEMICON COMPONENTS IND LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, in the case of using the formation process of the P-type well region to form the P-type base region, the impurity distribution in the base region becomes the same as the impurity distribution in the P-type well region, so it is not possible to obtain a V-NPN transistor. Desired properties, especially problems with hFE being smaller than expected

Method used

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  • Semiconductor device and method of manufacturing the same
  • Semiconductor device and method of manufacturing the same
  • Semiconductor device and method of manufacturing the same

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no. 1 approach 〕

[0052] figure 1 It is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention. figure 2 It is a top view of a V-NPN transistor of a semiconductor device. figure 2 The sectional view of the A-A line of figure 1 Corresponding to the cross-sectional view of the V-NPN transistor.

[0053] An N − -type epitaxial semiconductor layer 2 is formed on a semiconductor substrate 1 made of a P-type single crystal. The semiconductor substrate 1 and the N-type epitaxial semiconductor layer 2 form a PN junction. In the formation region of the NMOS transistor and the PMOS transistor, an N+ type buried layer 3A is formed across the PN junction of the semiconductor substrate 1 and the N-type epitaxial semiconductor layer 2, so as to reduce the N-type epitaxial semiconductor layer 2 (PMOS transistor) substrate) resistance.

[0054] In addition, in the formation region of the V-NPN transistor, an N+-type buried layer 3B is formed across ...

no. 2 approach 〕

[0081] Figure 4 It is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention. This embodiment and the first embodiment ( figure 1 ) in that the N − -type emitter region 12E having a lower concentration than the N + -type emitter region 14E is formed in contact with the bottom of the N + -type emitter region 14E. In order to rationalize the process, the N + -type emitter region 14E is preferably formed using the process of forming the N + -type source layer 14S and the N + -type drain layer 14D of the NMOS transistor (ion implantation of N-type impurities). The N − -type emitter region 12E is preferably formed using the steps of forming the N − -type source layer 12S and the N − -type drain layer 12D of the NMOS transistor (ion implantation of N-type impurities).

[0082] The N-type source layer 12S and the N-type drain layer 12D of the NMOS transistor are formed deeper than the N+-type source layer 14S and the N+-type drai...

no. 3 approach 〕

[0087] Figure 5 is a cross-sectional view of a semiconductor device according to a third embodiment of the present invention. This embodiment and the second embodiment ( Figure 4 ) in that the P + -type base region 11B is formed in contact with the bottom of the N − -type emitter region 12E and has an increased concentration of the P-type base region 7 . In order to rationalize the process, the P+-type base region 11B is preferably formed using the process of forming the deep P-type source layer 11S and P-type drain layer 11D of the PMOS transistor (ion implantation of P-type impurities such as boron).

[0088] In order to form the P-type source layer 11S and the P-type drain layer 11D deeper than the P+-type source layer 13S and the P+-type drain layer 13D, for example, the P-type source layer 11S and the P-type drain layer 11D is formed by ion implantation of boron, and the P+ type source layer 13S and P+ type drain layer 13D are formed by ion implantation of boron diflu...

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Abstract

The invention provides a semiconductor device and a method of manufacturing the same. The semiconductor device is manufactured by a BiCMOS process in which a process of manufacturing a V-NPN transistor is rationalized. Furthermore, the hFE of the transistor is adjusted to a large value. An N type base width control layer (9) is formed being in contact with a bottom portion of a P type base region (7) under an N+ type emitter region (14E). The N type base width control layer (9) shallows a portion of the P type base region (7) under the N+ type emitter region (14E) partially. The P type base region (7) is formed by using a process of forming a P type well region (6), and the N type base width control layer (9) is formed by using a process of forming an N type well region (8), thereby achieving the process rationalization.

Description

technical field [0001] The present invention relates to a semiconductor device manufactured by a BiCMOS process and a method of manufacturing the same. Background technique [0002] Conventionally, it is known that P-channel MOS transistors (hereinafter referred to as PMOS transistors), N-channel MOS transistors (hereinafter referred to as NMOS transistors) and vertical NPN bipolar transistors are formed on one semiconductor substrate by a BiCMOS process. (hereinafter referred to as a V-NPN transistor) semiconductor device. Such a semiconductor device is described in Patent Document 1. [0003] In this case, a dedicated process for forming the P-type base region of the V-NPN transistor is provided, and the characteristics of the V-NPN transistor, especially hFE (direct current amplification factor) are adjusted to desired values. In addition, in order to rationalize the process, the P-type base region may be formed using the formation process of the P-type well region with...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/06H01L21/8249
CPCH01L29/66272H01L29/7322H01L21/8249H01L29/1004H01L27/0623
Inventor 大竹诚治
Owner SEMICON COMPONENTS IND LLC
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