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Transistor and forming method thereof

A transistor and semiconductor technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as poor performance, achieve better performance, reduce time, and improve performance.

Active Publication Date: 2012-11-14
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] However, existing trench metal-oxide-semiconductor field effect transistors perform poorly

Method used

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  • Transistor and forming method thereof
  • Transistor and forming method thereof
  • Transistor and forming method thereof

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Experimental program
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Effect test

Embodiment Construction

[0047] As mentioned in the background, existing trench metal-oxide-semiconductor field effect transistors have poor performance.

[0048] The inventor of the present invention finds through research, please refer to Figure 5 , in the prior art, after forming the mask layer 104, a conductive plug 106 (such as Figure 4 ) before, using the mask layer 104 as a mask, ion implantation is performed on the semiconductor substrate 100 on both sides of the trench, and thermal annealing is performed to activate the implanted ions to form a source region 105; however, after thermal annealing When the implanted ions are activated, the horizontal diffusion rate of the ions is lower than the vertical diffusion rate; specifically, the lateral diffusion rate of the dopant ions is 60-80% of the vertical diffusion rate; therefore, in order to make the formed source region 105 and gate The contact between the dielectric layer 102 will make the thermal annealing time longer, resulting in the di...

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Abstract

Provided are a transistor and a forming method thereof. The transistor comprises a semiconductor substrate, a groove located in the semiconductor substrate, a gate dielectric layer located on the lateral wall and the bottom surface of the groove, a gate electrode layer located on the surface of the gate dielectric layer, a source region and a drain region. The groove is formed by a first sub groove and a second sub groove located below the first sub groove, wherein the second sub groove is communicated with the first sub groove, an opening of the first sub groove is larger than that of the second sub groove, the lateral wall of the first sub groove is inclined relative to the surface of the semiconductor substrate, and the lateral wall of the second sub groove is perpendicular to the surface of the semiconductor substrate. The gate electrode layer fully fills the groove and the surface of the gate electrode layer is level to that of the semiconductor substrate. The source region is located in the semiconductor substrate on two sides of the groove. The drain region is located in the semiconductor substrate on one side opposite to the groove and is opposite to the second sub groove. The transistor is stable in threshold voltage and good in performance.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a transistor and a forming method thereof. Background technique [0002] At present, transistors are widely used as a basic semiconductor device. Among various transistors, Trench Metal-Oxide-Silicon Transistors (Trench Metal-Oxide-Silicon Transistors), as a power device, are widely used in VLSI. [0003] Schematic diagram of the cross-sectional structure of the formation process of the existing trench metal-oxide-semiconductor field effect transistor, such as Figure 1 to Figure 4 shown, including: [0004] Please refer to figure 1 , provide a semiconductor substrate 100 , the semiconductor substrate 100 has a trench 101 inside, and the sidewall of the trench 101 is perpendicular to the surface of the semiconductor substrate 100 . [0005] Please refer to figure 2 , in the trench 101 (as figure 1 ) to form a gate dielectric layer 102 on the sidewall a...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/423H01L29/78H01L21/28H01L21/336
Inventor 楼颖颖
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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