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SRAM (Static random access memory) bit line leakage current compensation circuit

A technology for compensating circuits and leakage currents, applied in information storage, static memory, digital memory information, etc., can solve the problems of SRAM performance degradation and achieve the effect of eliminating adverse effects

Inactive Publication Date: 2012-07-18
ANHUI UNIVERSITY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] For the problem of large leakage current on the bit line, K. Agawa, H. Hara, T. Takayanagi, and T. Kuroda wrote in 2001 a JSSC titled "A Bitline Leakage Compensation Scheme for Low-Voltage SRAMs" The article clarifies the bit line leakage current compensation circuit proposed by it. Although the compensation circuit with this structure can realize the compensation purpose of the bit line leakage current in theory, it can eliminate the disadvantages caused by the large leakage current in the circuit to the SRAM circuit. However, because it uses a leakage current compensation method that detects the leakage current in advance and then fully compensates, there may be a problem of SRAM performance degradation in actual circuit implementation.

Method used

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  • SRAM (Static random access memory) bit line leakage current compensation circuit
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  • SRAM (Static random access memory) bit line leakage current compensation circuit

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Embodiment Construction

[0014] The SRAM bit line leakage current compensation circuit of the present invention is used as an auxiliary circuit of the SRAM circuit, and two identical compensation circuits are provided to jointly realize the auxiliary compensation of the SRAM circuit (main circuit). Each compensation circuit ( figure 1 ) includes five PMOS transistors P1~P5 and six NMOS transistors N1~N6; the source terminals of the PMOS transistors P1~P5 are respectively connected to their respective body terminals and connected to the power supply voltage VDD, and the body terminals of the NMOS transistors N1~N6 are connected to The power ground VSS, the source end of NMOS transistor N1, the source end of NMOS transistor N2, and the source end of NMOS transistor N6 are all connected to their respective body ends, the drain end of PMOS transistor P1 is connected to the drain end of NMOS transistor N1, and the drain end of PMOS transistor P1 The gate terminal of the PMOS transistor P2, the drain termi...

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Abstract

The invention discloses an SRAM (static random access memory) bit line leakage current compensation circuit as an auxiliary circuit of an SRAM circuit. The SRAM bit line leakage current compensation circuit comprises two completely same compensation circuits which are utilized together for auxiliary compensation of the SRAM main circuit, wherein each compensation circuit is provided with two input / output ends and a control signal CON which is used for controlling the operation pattern of the bit line leakage current compensation circuit; each current compensation circuit comprises 5 PMOS (P-channel metal oxide semiconductor) and 6 NMOS (N-channel metal oxide semiconductor); through detecting the variation conditions of the electric potential variation ratio on two bit lines in the main circuit under the normal operation state, the compensation circuit automatically enables signals of a bit line at one end, which discharges slowly, to discharge more slowly, and enables the signals of a bit line at one end, which discharges quickly, to discharge more quickly, thus the influences to the main circuit by greater leakage current on the SRAM bit line are eliminated, and help is provided for the correct recognition of the subsequent circuit signals.

Description

technical field [0001] The invention relates to a SRAM bit line leakage current compensation circuit, which belongs to the technical field of integrated circuit design. Background technique [0002] In today's SRAM (static random access memory) applications, more and more problems will continue to be highlighted with the continuous advancement of technology. One of the important problems is that the leakage current in SRAM will increase exponentially with the continuous decrease of the device threshold voltage. Although the existence of leakage current in the SRAM circuit is inevitable, the impact of excessive leakage current on the SRAM cannot be ignored. When there is a large bit line leakage current in the SRAM circuit, it will cause a gap between the two bit lines. The reduction of the voltage difference will cause the subsequent circuit to fail to correctly identify the signal, especially the excessive leakage current of the bit line will have a non-negligible impact o...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/413
Inventor 谭守标吴秀龙柏娜李正平孟坚陈军宁徐超高珊李瑞兴
Owner ANHUI UNIVERSITY
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