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Single-end-operated subthreshold storage unit circuit

A memory cell circuit, sub-threshold technology, applied in information storage, static memory, digital memory information and other directions, can solve the problem of difficult writing of memory cells, and achieve improved stability, improved anti-noise capability, and enhanced robustness. Effect

Inactive Publication Date: 2012-07-18
ANHUI UNIVERSITY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, it should be noted that the storage unit with single-ended operation will also have problems such as difficulty in writing

Method used

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  • Single-end-operated subthreshold storage unit circuit
  • Single-end-operated subthreshold storage unit circuit
  • Single-end-operated subthreshold storage unit circuit

Examples

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Embodiment Construction

[0022] see figure 1 , The storage unit circuit of the present invention is provided with two PMOS transistors P1, P2 and seven NMOS transistors N1-N7. The body terminals of the two PMOS transistors are connected to the power supply voltage Vdd, and the body terminals of the seven NMOS transistors are grounded; the source of the PMOS transistor P1 is connected to Vdd, and the drain of the PMOS transistor P1 is connected to the drains of the NMOS transistors N3 and N4 Together, the sources of NMOS transistors N3 and N4 are connected together and then connected to the drain of NMOS transistor N1, the source of N1 is grounded, and the gates of PMOS transistor P1 and NMOS transistor N1 are connected together to NMOS transistor N2 and PMOS transistor The drain of P2 is connected, the gate of NMOS transistor N3 is connected with row write control signal RWR, the gate of NMOS transistor N4 is connected with column write control signal CWR; NMOS transistor N2 and PMOS transistor P2 for...

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Abstract

The invention discloses a single-end-operated subthreshold storage unit circuit, comprising two PMOS (P-channel Metal Oxide Semiconductor) transistors, namely P1 and P2, and seven NMOS (N-channel Metal Oxide Semiconductor) transistors, namely N1-N7, wherein the body ends of P1 and P2 are connected with a voltage drain-drain Vdd after being connected with the respective sources; the body ends of N1-N7 as well as the sources of N1, N2 and N7 are all grounded; the grid of N3 is connected with a row-writing control signal RWR; the grid of N4 is connected with a column-writing control signal CWR; an inverter is composed of N2 and P2; the output end of the inverter is connected with the grids of N2 and P2; the input end of the inverter is connected with the drain of P1; the grid of the N5 is connected with a reading word line RWL; the drain of N5 is connected with a reading bit line RBL; the source of N6 is connected with a writing bit line WBL; and the grid of N6 is connected with a word writing line WWL.

Description

technical field [0001] The invention relates to a single-end operation sub-threshold storage unit circuit working in a sub-threshold region, and belongs to the technical field of integrated circuit design. Background technique [0002] The memory cell array is an important part of modern system-on-chip (SOC), and it is often the bottleneck of system design. As the market's requirements for portable devices continue to increase, the power consumption of memory cell arrays must also be reduced. Sub-threshold design is a hotspot in the ultra-low power consumption design of storage arrays. By reducing the supply voltage (Vdd) into the sub-threshold region of the circuit - Vdd is less than the threshold voltage (Vth), the dynamic and static power consumption of the system is significantly reduced. The design of the subthreshold memory cell array especially shows the excellent performance of the subthreshold design in terms of low power consumption. [0003] With the continuous...

Claims

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Application Information

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IPC IPC(8): G11C11/413
Inventor 吴秀龙柏娜谭守标李正平孟坚陈军宁徐超代月花龚展立
Owner ANHUI UNIVERSITY
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