High-voltage-resistant tunneling field effect transistor (TFET) and preparation method thereof

Abstract

The invention provides a high-voltage-resistant tunneling field effect transistor (TFET) and a preparation method thereof. The TFET comprises a semiconductor substrate, a channel region, a first buried layer, a second buried layer, a source region, a drain region, a gate dielectric and a gate, wherein the channel region is formed in the semiconductor substrate and comprises one or more shallow trench isolations (STI); the first buried layer and the second buried layer are formed in the semiconductor substrate and are positioned on two sides of the channel region respectively; the first buried layer has the first non-heavy doping type; the second buried layer has the second non-heavy doping type; the source region and the drain region are formed in the semiconductor substrate and are positioned on the first buried layer and the second buried layer respectively; the source region has the first heavy doping type; the drain region has the second heavy doping type; the gate dielectric is formed on the STI of the channel region; and the gate is formed on the gate dielectric. The STI is arranged in an active region of the substrate so as to enlarge a superficial area of a channel, and the effect is equivalent to that of elongating the channel; and therefore, the high-voltage resistance of the TFET is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor design and manufacture, in particular to a tunneling transistor with high breakdown voltage and a preparation method thereof. Background technique [0002] For MOSFET (Metal Oxide Semiconductor Field Effect Transistor) integrated circuits, the off-state leakage current rises rapidly as the size of the integrated circuit shrinks. In order to reduce the leakage current, thereby further reducing the power consumption of the device and improving the withstand voltage capability of the device, and Tunneling transistors (TFETs) with different operating principles from MOSFETs are widely used. At present, the drain and the source of a conventional tunneling transistor are located on the same plane of the semiconductor substrate. The tunneling transistor with this structure has poor high voltage resistance, large on-resistance, and high power consumption. Therefore, how to improve the withstand vol...

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Problems solved by technology

[0003] The purpose of the present invention is to at least solve one of the above-mentioned technical defects, especially to solve the shortcomings of existing tunneling transistors such as poor high voltage resistance, large on-resistance, and high power consumption.

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