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Low-voltage high-speed frequency divider

A frequency divider, low-voltage technology, applied in the direction of electrical components, automatic power control, etc., can solve the problems of reducing the minimum value of the power supply voltage of the frequency divider, complex circuit structure, etc.

Inactive Publication Date: 2012-07-04
杭州中科微电子有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0012] The purpose of the present invention is to overcome the very complex defects of the technology and circuit structure of the prior art, disclose a kind of high-speed, low-voltage high-speed frequency divider, its circuit structure is comparatively simple, and it is better than traditional static load source coupled latch structure In addition to the clock input transistor, the source-drain voltage V of a transistor is omitted dS1 , which can effectively reduce the minimum value of the supply voltage required by the frequency divider

Method used

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Examples

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Effect test

no. 1 Embodiment

[0077] The tube-level schematic diagram of the basic circuit structure of the low-voltage high-speed frequency divider of the present invention is as follows: Figure 2a shown. The low-voltage high-speed divider consists of two identical latches 2-1 and 2-2 cross-coupled with clocked transistors. The first latch 2-1 with clocked transistors includes: a sampling differential pair amplifier 21 composed of M 1 and M 2 composed of a latched cross-coupled pair amplifier 22 consisting of M 3 and M 4 composed, as the load module 23 consists of the load tube M P1 ,M P2 and clock control tube M C1 composition. The second latch 2-2 with clocked transistors includes a sampling differential pair amplifier 24 composed of M 5 and M 6 composed of a latched cross-coupled pair amplifier 25 consisting of M 7 and M 8 composed, as the load module 26 consists of the load tube M P3 ,M P4 and clock control tube M C2 composition.

no. 2 Embodiment

[0079] For the tube-level structure composition diagram of another latch 2-1 with a low-voltage clocked transistor, see Figure 2b . The differential signals CN and CP from the front-end VCO or other devices are added to the drain of the tail current source after passing through the DC blocking capacitor, the differential signal CN is also connected to the source of the sampling differential pair 21, and the differential signal CP is also connected to The source of the differential pair transistor 22 is latched. The differential signal input terminals of the sampling differential pair tube 21 of the latch with clocked transistor 2-1 are IP and IN, the cross-coupled output terminals of the latch cross-coupled pair tube 22 are QP and QN, and the cross-coupled output terminals QP and QN is connected to the load module 23 clock control tube MC in parallel 1 source and drain of the load module 23 Z 1 and Z 2 is the load tube, load tube Z 1 ,Z 2 and clock control tube MC 1 Ca...

no. 3 Embodiment

[0081] Such as image 3 Shown is the composition circuit diagram of the low-voltage high-speed frequency divider of the third embodiment. The low-voltage high-speed frequency divider includes a first latch 3-1 and a second latch 3-2. The first latch consists of the M 1 and M 2 consists of 31 sampled differential pairs and consists of M 5 and M 6 Composed of 32 latched cross-coupled pairs, the MP 1 , MP 2 and clock control tube MC 1 The composed load module 33 also includes a first tail current source. The second latch consists of the M 5 and M 6 The sampling differential pair consists of tube 34, and consists of M 7 and M 8 composed of 35 latched cross-coupled pairs, consisting of MP 3 , MP 4 and clock control tube MC 2 Consisting of load module 36, also includes a second tail current source. image 3 , amplifier M 1 ~ M 8 All are NMOS tubes, the MP in the load module 1 ~MP 4 and clock control tube MC 1 ~MC 2 All are PMOS tubes. The clock signal CP passes ...

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Abstract

The invention discloses a low-voltage high-speed frequency divider. A clock control tube is arranged at two ends of load output so as to form a low-supply-voltage frequency divider with clock-controlled transistors. Compared with the circuit structure of the conventional frequency divider, the low-voltage high-speed frequency divider does not need a clock input differential pair tube, and reduces the limitation on the minimum value of a supply voltage. The low-voltage high-speed frequency divider comprises two latches with the same circuit structure, wherein a clock-controlled transistor which is controlled by same-direction clock signals is connected to two output ends of each latch respectively; and the dynamic load of each latch with the clock-controlled transistor is low in resistance in a sampling stage to reduce charging and discharging time, so that the conversion speed is greatly increased, the working frequency is increased, the defect that a quiescent bias point of the conventional dynamic load structure changes is overcome, and the dynamic load is high in resistance value in a latching stage to provide enough gains. One more control dimension is added to the low-voltage high-speed frequency divider, and compared with the conventional latch, the low-voltage high-speed frequency divider is higher in working frequency and wider in working range, and is more adaptive to a low supply voltage.

Description

[0001] Field [0002] The invention belongs to the technical field of integrated circuit signal processing, and relates to a frequency divider with a clock-controlled transistor, in particular to a low-voltage high-speed frequency divider, a phase-locked loop for a wireless radio frequency synthesizer and corresponding products. technical background [0003] The source-coupled logic circuit is evolved from the ECL structure of the bipolar circuit. Due to the small swing of the circuit, the working speed of the circuit is improved. Source-coupled logic (SCL) frequency divider occupies an important proportion in high-speed CMOS frequency division circuits due to its advantages of wide operating range and suitable power consumption. The key to limit the speed of the source coupling circuit is the load resistance. A small load resistance is beneficial to reduce the time constant, and a large resistance is beneficial to the amplification of the signal. In order to meet the require...

Claims

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Application Information

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IPC IPC(8): H03L7/18
Inventor 于云丰潘文光庄海孝马成炎
Owner 杭州中科微电子有限公司
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