Dictionary coding compression method

Abstract

A dictionary coding compression method without the storage of a dictionary contains the following steps of: a, generating a determined complete test set by the adoption of an automatic test mode generation tool and recoding the test vector number as N; b, cascading all the test vectors, namely cascading the tail of a vector with the head of another vector, and recording as S; c, establishing an irrational number dictionary list, beginning integers a and b with 2, storing the first t values of the continuously calculated values according to a binary system, establishing a dictionary with the corresponding index being a and b until a=m and b=n, wherein t, m and n are all integers and the values are adjusted according to an actual compression situation; d, coding, carrying out bitwise comparison between S from the beginning and the dictionary list, taking the longest one which is compatible with the dictionary list, recording the corresponding compatible length k and the corresponding indexes x and y, removing the front k values from S, and repeating the step d until S is empty. The invention has the following advantages: memory capacitance is greatly minimized, unrelated bit stuffing is not required, and the efficiency is high.

Description

【Technical field】 [0001] The invention relates to an integrated circuit test technology, in particular to a test data compression method in a built-out self-test (Built-Out Self-Test, BOST) method for a system chip (System-on-a-Chip, SoC). 【Background technique】 [0002] The development of integrated circuit technology makes it possible to integrate hundreds of millions of devices in one chip, and can integrate pre-designed and verified IP, such as memory, microprocessor, DSP (digital signal processor) and so on. This diversified integrated chip has become an integrated system capable of processing various information, and is called a system-on-chip or system-on-a-chip. SoC greatly reduces the system cost, shortens the design cycle, and speeds up the time to market, but the testing of SoC products faces more and more challenges, such as: [0003] 1. There are few test points on the chip, and the test points that can be directly controlled or observed are limited. Usually, i...

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Problems solved by technology

[0003] 1. There are few test points on the chip, and the test points that can be directly controlled or observed are limited. Usually, it can only be tested through the limited input / output pins of the chip, and it is difficult to directly control or observe the internal nodes of the chip through macro mechanical devices.

[0004] 2. Automatic test equipment (ATE) is expensive, and the development speed of chip design and manufacturing technology is faster than that of ATE. The clock frequency of the chip has exceeded the frequency of the most advanced ATE at present, and full-speed testing cannot be performed.

[0005] 3. The amount of test data is large. The more IP integrated in the SoC, the greater the amount of test data required

[0014] The current dictionary encoding needs to store dictionary and index information, which occupies a certain storage capacity

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