True Single-Phase Clock (TSPC) 2/3 dual-mode prescaler with high speed and low power consumption

Abstract

The invention discloses a True Single-Phase Clock (TSPC) 2 / 3 dual-mode prescaler with a high speed and low power consumption. The TSPC 2 / 3 dual-mode prescaler comprises six-stage dynamic phase inverters, a D trigger DFF1 in a TSPC structure which is formed by serially connecting a first-stage dynamic phase inverter, a second-stage dynamic phase inverter and a third-stage dynamic phase inverter and a D trigger DFF2 in a TSPC structure which is formed by serially connecting a fourth-stage dynamic phase inverter, a fifth-stage dynamic phase inverter and a sixth-stage dynamic phase inverter. The TSPC 2 / 3 dual-mode prescaler with the high speed and the low power consumption, disclosed by the invention, removes an AND gate and an OR gate in the traditional TSPC 2 / 3 dual-mode prescaler structure and directly sends outputs of the first D trigger to the fifth-stage dynamic phase inverter in the second D trigger to control pre-charge from the fifth-stage dynamic phase inverter to a node P2 and delay high electric level output by the 2 / 3 dual-mode prescaler for one more clock period. Therefore, three-way frequency division operation is realized and working speed for the three-way frequency division of the 2 / 3 dual-mode prescaler is improved.

Description

technical field [0001] The invention relates to frequency divider technology, in particular to a high-speed and low-power true single-phase clock (TSPC) 2 / 3 dual-mode prescaler. Background technique [0002] The dual-mode prescaler is a frequency division device with two controllable frequency division ratios. It is an important part of the phase-locked loop. According to the different mode control signals and a specific frequency division ratio, the input high-frequency clock The signal is frequency-divided into a low-frequency clock signal. In the phase-locked loop, the dual-mode prescaler divides the high-frequency signal of the voltage-controlled oscillator into a low-frequency clock signal. It has the highest operating frequency and the largest power consumption in the phase-locked loop. module. [0003] The frequency divider in the phase-locked loop consists of a dual-modulus prescaler, a program counter and a swallow counter. The output signal of the voltage-control...

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Problems solved by technology

[0004] The synchronous N / N+1 frequency divider based on dynamic circuit technology is an implementation structure of the dual-mode prescaler. A commonly used dual-mode frequency divider is a synchronous 2 / 3 dual-mode prescaler. Other N The / N+1 dual-mode frequency divider can be designed with the 2 / 3 dual-mode prescaler as the core. In the synchronous 2 / 3 dual-mode prescaler, the feedback control composed of logic such as OR gate and AND gate is added. , the working speed will be much slower than that of the divider by two, and will consume most of the power consumption of the divider

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