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DC offset cancellation circuit

A technology for eliminating circuit and DC offset, applied in the direction of DC level restoration device/bias distortion correction, baseband system components, etc. layout area, improve integration, eliminate the effect of DC offset

Inactive Publication Date: 2011-07-20
UNIV OF ELECTRONIC SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to solve the shortcoming that the equivalent high-pass cut-off frequency of the above-mentioned DC offset elimination circuit cannot be adjusted, and propose a DC offset elimination circuit

Method used

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Embodiment Construction

[0011] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0012] Such as figure 1 As shown, a DC offset elimination circuit includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first feedback capacitor C1, a second feedback capacitor C2, a first voltage control signal port VC1, the second voltage control signal port VC2, the signal input positive terminal Vip, the signal input negative terminal Vin, the signal output positive terminal Vop, the signal output negative terminal Von and the operational amplifier Op-amp, wherein the drain of the first transistor M1 is connected to The signal input positive terminal Vip is connected, the source of the first transistor M1 is connected with the positive input terminal ip of the operational amplifier Op-amp; the drain of the second transistor M2 is connected with the signal input negative terminal Vin, and th...

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Abstract

The invention discloses a DC offset cancellation circuit, which comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a first feedback capacitor, a second feedback capacitor, a first voltage control signal port, a second voltage control signal port, a signal input positive end, a signal input negative end, a signal output positive end, a signal output negative end and an operational amplifier. A first voltage control signal controls the resistance of equivalent resistors of the first and second transistors, and a second voltage control signal controls the resistance of the equivalent resistors of the third and fourth transistors to fulfill the aim of adjusting equivalent high pass off frequency; therefore, the DC offset cancellation circuit can reduce damages to useful low frequency components in the signals as much as possible at the same time of suppressing or canceling DC offset. The DC offset cancellation circuit adopts active resistors instead of passive resistors, so the area of a circuit layout is reduced, and the level of integration of the circuit is improved.

Description

technical field [0001] The invention belongs to the field of radio frequency integrated circuits, in particular to a DC offset elimination circuit. Background technique [0002] With the rapid development of complementary metal oxide semiconductor (CMOS, Complementary Metal Oxide Semiconductor) technology and the continuous expansion of people's demand for wireless communication, wireless communication receivers have been more and more widely used. In order to receive signals with a large dynamic range, wireless communication receivers need to have high linearity to correctly receive demodulated strong signals, and zero-IF receivers have the characteristics of small size, low cost, and multi-band multi-mode compatibility. It has become a very competitive structure in wireless communication receivers. At present, some mature mobile terminal equipment front-end design schemes adopt this structure. [0003] Although the zero-IF structure has many advantages, it also has its ow...

Claims

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Application Information

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IPC IPC(8): H04L25/06
Inventor 文光俊冯筱杨拥军杨洲
Owner UNIV OF ELECTRONIC SCI & TECH OF CHINA
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