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Sub-threshold storage array circuit

A storage array and sub-threshold technology, which is applied in the direction of information storage, static memory, digital memory information, etc., can solve the problems of memory unit circuit chip area consumption, inability to adapt to sub-threshold circuits, and the influence of turn-on current, achieving low power consumption, High robustness, effect of maintaining noise margin

Inactive Publication Date: 2012-12-19
SOUTHEAST UNIV
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  • Claims
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AI Technical Summary

Problems solved by technology

[0005] The problem to be solved by the present invention is: in the sub-threshold storage circuit, the ratio of the opening and closing current of the storage unit to I on / I off Smaller, the leakage current of the matching transistor of the unselected memory cell on the bit line has a great influence on the turn-on current of the selected memory cell, and the existing solutions all have the problem of excessive consumption of memory cell circuit chip area, conventional design The method of simply using the bit line leakage current compensation can not meet the needs of sub-threshold circuit design.

Method used

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Embodiment Construction

[0023] see figure 1 , the high-density, high-robust subthreshold memory cell bit line on-off current ratio compensation design of the present invention includes a pseudo-current mirror compensation design and a writable sense amplifier design. The overall block diagram of the sub-threshold memory array circuit is that a certain number of memory cells are connected in series between two bit lines, and a booster circuit, a precharge / balance circuit, and a write enable circuit are connected in parallel between the two bit lines in sequence from the memory cell array to the outside. capable circuits and sense amplifier circuits.

[0024] For write-back sense amplifiers such as figure 2 , there are five PMOS transistors P1, P2, P3, P4, P5 and six NMOS transistors N1, N2, N3, N4, N5, N6. The body ends of all NMOS transistors N1~N6 are connected to the ground, and the body ends of all PMOS transistors P1~P5 are connected to the power supply voltage Vdd; the source end of PMOS tran...

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Abstract

The invention relates to a sub-threshold storage array circuit. A plurality of storage units are connected in series between two bit lines in a sub-threshold area; an enhancing circuit, a pre-charging / balancing circuit, a write enabling circuit and a sensitive amplifier circuit are connected in parallel between the two bit lines in turn; the sensitive amplifier circuit comprises a sensitive amplifier capable of writing back; and in the enhancing circuit, a pseudo-current mirror compensating circuit is taken as a leakage current compensating circuit. The invention overcomes the defects in the prior art and provides a sub-threshold storage unit bit line current compensating and read-write enhancing circuit with high density and robustness to balance the indexes of the storage units and achieve optimal system performance.

Description

technical field [0001] The invention relates to a storage unit under a subthreshold working area, leakage current compensation in a subthreshold storage unit array circuit, and a subthreshold sensitive amplifier circuit, which is a subthreshold storage array circuit. Background technique [0002] Memory cell arrays are an important part of modern digital systems, and are often the bottleneck of power consumption in system design. The continuous improvement of the market's demand for various portable devices puts forward higher requirements for the power consumption reduction technology of the memory cell array. Sub-threshold design is currently a hot topic in ultra-low power consumption design. Sub-threshold design enters the sub-threshold region of the circuit by reducing the power supply voltage Vdd: Vdd is less than the threshold voltage Vth, making the system work in the sub-threshold region of the circuit, thereby significantly reducing the dynamics of the system. ,Sta...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/414
Inventor 时龙兴柏娜蔡志匡朱贾峰李瑞兴
Owner SOUTHEAST UNIV
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