High-robustness subthreshold memory cell circuit for limiting drain current

A memory cell circuit and threshold technology, which is applied in information storage, static memory, digital memory information and other directions, can solve the problem of process deviation of memory cells, and achieve the effect of reducing leakage current power consumption

Inactive Publication Date: 2012-06-27
SOUTHEAST UNIV
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

However, the reduction of the power supply voltage will make the memory cell affected by the process deviation

Method used

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  • High-robustness subthreshold memory cell circuit for limiting drain current
  • High-robustness subthreshold memory cell circuit for limiting drain current
  • High-robustness subthreshold memory cell circuit for limiting drain current

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Experimental program
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Effect test

Embodiment Construction

[0029] see figure 2 :

[0030] A. Write operation

[0031] Due to the decrease of the overdrive voltage of the circuit in the sub-threshold region, the increase of the load capacitance and the instability of the process, it is difficult for the sub-threshold memory cell to maintain sufficient write noise margin. The subthreshold memory cell designed in this paper can effectively improve the writability of the memory cell by utilizing the internal positive feedback of the memory cell destroyed during the writing process and weakening the pull-down ability.

[0032] Let the initial value of the storage unit be: Q="0", Q is not a point Assuming a "0" is written to the Q NOT node, the bit line BL and the bit line NOT NBL are forced to "1" and "0". The word line WL becomes high level, Q non-dot Discharge until the P1 tube is turned on. In this way, the source terminal of N1 and the potential of point Q, Vgs="0", N1 is turned off. This advantageously breaks the feedback loo...

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Abstract

The invention relates to a high-robustness subthreshold memory cell circuit for limiting a drain current, which comprises two PMOS pipes P1 and P2, ten NMOS pipes N1-N10 and twelve transistors, wherein P1, N3 and N5 and P2, N4 and N6 respectively form a first phase inverter and a second phase inverter; the two phase inverters are in cross-coupling connection; turn-off pipes N1 and N2 are used forconnecting the two phase inverters to a power access; feedback pipes N7 and N8 automatically regulate the upset threshold voltage of the two phase inverters according to input signals; N9 and N10 arematching transistors of a memory cell; any one of the source terminal and the drain terminal of the N9 is connected with the output terminal of the first phase inverter, while the other terminal is connected with a bit line; any one of the source terminal and the drain terminal of the NMOS pipe N10 is connected with the output terminal of the second phase inverter, while the other terminal is connected with a bit line NOT; and gate terminals of the N9 and the N10 are respectively connected with a word line.

Description

technical field [0001] The invention relates to a storage unit under a sub-threshold working region, in particular to a highly robust sub-threshold storage unit circuit with leakage current limitation. It can further reduce the minimum energy consumption point of the memory cell array to about 200mV, and is the memory cell with the lowest energy consumption in the currently known memory cell array. Background technique [0002] Memory cell arrays are an important part of modern digital systems, and are often the bottleneck of power consumption in system design. The continuous improvement of the market's demand for various portable devices puts forward higher requirements for the power consumption reduction technology of the memory cell array. [0003] Sub-threshold design is currently a hot topic in ultra-low power design. By reducing the power supply voltage (Vdd) into the sub-threshold region of the circuit—Vdd is less than the threshold voltage (Vth), the system works i...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/40
Inventor 柏娜陈鑫邓小莺杨军时龙兴
Owner SOUTHEAST UNIV
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