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ESD protective circuit with control circuit for integrated circuit

An ESD protection and integrated circuit technology, applied in the electronic field, can solve the problem of occupying the silicon chip area, etc., and achieve the effect of reducing the trigger voltage and reducing the phenomenon of false triggering

Inactive Publication Date: 2011-01-12
UNIV OF ELECTRONIC SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Moreover, general chips have many pins. If each MOS used for ESD protection uses a trigger control circuit, it will inevitably occupy a large amount of silicon chip area.

Method used

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  • ESD protective circuit with control circuit for integrated circuit
  • ESD protective circuit with control circuit for integrated circuit
  • ESD protective circuit with control circuit for integrated circuit

Examples

Experimental program
Comparison scheme
Effect test

specific Embodiment approach 1

[0024] An ESD protection circuit with a control circuit for an integrated circuit, such as Figure 4As shown, it includes a control circuit 3 , a protection circuit 4 and an ESD power supply clamping circuit 6 . The control circuit 3 is composed of an RC trigger circuit 1 and an inverter group 2; the VDD rail in the dual rails of the integrated circuit power supply is connected in series with the VSS rail in the dual rails of the integrated circuit power supply through the RC trigger circuit 1 formed by series connection of a resistor R and a capacitor C ; The inverter group 2 is formed in series by the first-stage inverter 7 and the second-stage inverter 8; The input ends of the first-stage inverter 7 are connected, and the output end of the first-stage inverter 7 is connected with the input end of the second-stage inverter 8 . The protection circuit 4 is realized by complementary NMOS transistors and PMOS transistors, wherein a PMOS transistor is connected between each I / O ...

specific Embodiment approach 2

[0032] An ESD protection circuit with a control circuit for an integrated circuit, such as Figure 9 As shown, it includes a control circuit 3 , a protection circuit 4 and an ESD power supply clamping circuit 6 . The control circuit 3 is composed of an RC trigger circuit 1 and an inverter group 2; the VDD rail in the dual rails of the integrated circuit power supply is connected in series with the VSS rail in the dual rails of the integrated circuit power supply through the RC trigger circuit 1 formed by connecting the capacitor C and the resistor R in series ; The inverter group 2 is formed in series by the first-stage inverter 7 and the second-stage inverter 8; The input ends of the first-stage inverter 7 are connected, and the output end of the first-stage inverter 7 is connected with the input end of the second-stage inverter 8 . The protection circuit 4 is realized by complementary NMOS transistors and PMOS transistors, wherein a PMOS transistor is connected between each...

specific Embodiment approach 3

[0035] In the aforementioned two specific implementation methods, the number of stages of the inverter group can be increased from two stages to multiple stages, and the rest of the circuit structure remains unchanged, and the following can be obtained: Figure 10 The specific implementation shown. This particular embodiment increases the number of inverter stages in the inverter group 2, which can make the action of the trigger circuit faster when ESD occurs, but considering the area factor, the better choice is 3 or 4 , At the same time, the output of the last two stages of inverters should be reasonably selected, or the positions of R and C should be swapped to ensure correct level logic.

[0036] To sum up, the present invention provides a single control circuit to control a plurality of ESD protection circuit structure, which saves the silicon chip area occupied by the control circuit. At the same time, some auxiliary ESD discharge channels are provided outside the main ...

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Abstract

The invention discloses an ESD protective circuit with a control circuit for an integrated circuit, which belongs to the technical field of electronics. A plurality of ESD protective circuits of the invention are controlled by a single control circuit so as to save the area of a silicon chip occupied by the control circuit. Simultaneously, a plurality of auxiliary ESD relief passages are arranged besides a master ESD relief passage. The control circuit is utilized to reduce the triggering voltage of the ESD protective circuit, prevent an internal circuit device connected in parallel with an ESD protective device from being broken down and switched on first to further cause the anti-ESD capacity reduction of the chip and make more uniform the starting of an MOS device with a multi-finger structure.

Description

technical field [0001] The invention belongs to the field of electronic technology, and relates to the design technology of an electrostatic discharge (ESD for short) protection circuit of a semiconductor integrated circuit chip, in particular to a single control circuit to control multiple protection devices, so that the protection devices can be timely and effectively Discharge the ESD current, and at the same time save the silicon chip area occupied by the control circuit. Background technique [0002] With the reduction of device size in integrated circuits (Integrated Circuit, referred to as IC), the junction depth of the device is getting shallower and shallower, the gate oxide layer is getting thinner and thinner, and it has a lightly doped drain (LDD) structure. These changes make integration Circuits are more likely to be damaged by ESD. Therefore, protection circuits must be added to the chip to prevent IC circuits or devices from being damaged by ESD. [0003] A...

Claims

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Application Information

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IPC IPC(8): H01L27/04
Inventor 张波樊航蒋苓利韩山明刘娟
Owner UNIV OF ELECTRONIC SCI & TECH OF CHINA
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