Structure for implementing DFT of 32-channel parallel data

Abstract

The invention relates to a structure for implementing discrete Fourier transform (DFT) of 32-channel parallel data. In the invention, firstly, a full parallel structure is adopted, 32-channel parallel data is splitted into two 8-channel parallel data and a 16-channel data according to parity, secondly, a radix-2 butterfly algorithm is adopted to process the 8-channel parallel data, a radix-4 butterfly algorithm is utilized to process the 16-channel parallel data, finally the processed results of two 8-channel parallel data are multiplied by a constant coefficient, and addition and subtractionoperations are carried out with the processed result of the 16-channel parallel datum to obtain a DFT result of the 32-channel parallel data. The structure for implementing 32-channel parallel data DFT filters in a frequency domain, directly crosses over products, reduces delay time and amount of multipliers compared with a time domain multi-item filter method, decreases a processing scale of a field programmable gate array (FPGA) at the same time, improves hardware processing speed, is very suitable for processing high-speed and real-time digital signals, and can save hardware resource. The implementing structure can be completely utilized for carrying out inverse discrete Fourier transform (IDFT) on 32-channel parallel data.

Description

technical field [0001] The invention relates to a realization structure of 32-way parallel data DFT, which is mainly used in the field of high-speed digital processing, especially in the field of high-speed digital demodulators and modulators. Background technique [0002] For high-speed modulators, analog modulators are gradually developing towards digital modulators due to the flexibility of digital implementations such as shaping filtering and pre-distortion. The shaping filter in the high-speed digital modulator is divided into parallel look-up table and digital direct realization according to its implementation method. Since a parallel look-up table can only correspond to one shaping coefficient, for variable shaping coefficients, it is necessary to make many tables. It may not necessarily meet the requirements, which is not easy for FPGA implementation. However, the digital direct realization method has almost no influence on the realization of the variable molding co...

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Problems solved by technology

Since the analog processing method cannot achieve variable speed, and its debugging is more complicated, it has been gradually replaced by digital demodulation

For the demodulation of QPSK modulation signals with a code rate up to 600Mbps, according to the Nyquist sampling theorem, the sampling clock is as high as 1200MHz. Such a high sampling clock cannot be directly sent to the FPGA, and serial digital demodulation cannot be realized, only parallel digital demodulation

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