Video coder and coding method

Abstract

The invention discloses a video coder and a coding method, which belongs to the field of video coding. The coder is divided into five-stage flow modules comprising a data loading module, a first storage module, a whole pixel movement estimation module, a second storage module, a sub-pixel movement estimation module, a third storage module, an integrative processing module, a fourth storage module, a loop circuit filtering module and an entropy coding module. The invention also provides the video coding method. Data interaction between the five-stage flow modules is carried out by utilizing a dual-port memory module, the control logic of the data interaction is simplified, and the speed of data transmission between flow stages is enhanced. In the video coder, the data interaction between the stages is carried out in macroblock stages, data structures are consistent, the control procedure is simplified, the throughput rate is effectively enhanced, the delay is lowered, and real-time coding can be carried out on a video source with high definition.

Description

technical field [0001] The invention relates to the field of video encoding, in particular to a video encoder and encoding method. Background technique [0002] A video is a sequence consisting of a series of temporally related images. Each image in it is called a frame, and each frame can be divided into several blocks, usually a block is a square or a rectangle, and video coding takes a block as the basic unit for coding, and the commonly used blocks in video coding are 16×16, 8 ×16, 16×8, 8×8, 4×4, etc., the size of these blocks is in units of pixels, and pixels refer to the points that make up the image, which is the smallest unit of the image, and sub-pixels are processed by whole pixels. Generated by interpolation filtering, such as 1 / 2 or 1 / 4 pixels, etc. Video coding blocks can be divided into luma blocks and chrominance blocks according to the types of information they carry. In mainstream video coding standards, a set of luma blocks and chrominance blocks compose...

AI Technical Summary

Problems solved by technology

[0007] The data interaction between pipeline stages in the prior art mainly utilizes the bus or shared memory, but no matter the shared memory or the bus, it needs to be accessed by multiple modules through time division multiplexing, which may make some modules need to access When sharing memory or bus, it is necessary to wait for other modules to release the right to use the shared memory or bus, which seriously reduces the processing efficiency, affects the smoothness of the entire encoder operation, and affects the speed of data processing

[0008] The lack of an independent data loading module pipeline stage on the data path increases the burden of the first pipeline stage. Therefore, it significantly affects the throughput rate of the pipeline and slows down the speed of data processing.

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