Deskew device and method applied to high-speed parallel optical interconnection system

Abstract

The invention relates to a deskew device and method applied to a high-speed parallel optical interconnection system, which can be applied to a 40 Gbps very short distance optical transmission system. The frame alignment circuit of a deskew channel adopts a window comparator and a priority encoder, and determines the frame original position according to the search of frame delimiters, so as to realize the frame alignment. The data of each data channel is compared with the copy information of each data channel borne in the deskew channel after frame alignment so as to obtain the skewing amount of each data channel, and each data channel is aligned with the deskew channel, thereby achieving the alignment of 16 data channels. The fan-out of the circuit can be effectively reduced, the operating speed can be improved, and the device resource can be saved; moreover, a sliding window generator designed based on a shift register is matched with the window comparator to work, thereby being capable of adjusting the skewing amount among channels in wider range and improving the design flexibility and practicability.

Description

technical field [0001] The invention relates to a de-skewing circuit for a parallel optical interconnection system transmitting 40Gbps data rate at the physical layer, and in particular to a circuit structure realized based on a programmable logic device. Background technique [0002] With the increasing demand for information, the data transmission rate has generally exceeded 10Gb / s, whether it is in the central computer room of the backbone network, within the scope of the local area network based on 10 Gigabit Ethernet, or inside the equipment. . For this kind of high-speed data transmission in a short distance, electrical connection is no longer applicable, and the performance provided by the serial synchronous optical transmission network system applied to the long-distance backbone network is much higher than this demand, and the cost is relatively low. expensive. To this end, the Optical Internetworking Forum (OIF, Optical Internetworking Forum) has launched a Very ...

AI Technical Summary

Problems solved by technology

However, limited by the system clock, the 2.488Gb / s data in the SFI-5 interface must be serial-parallel converted into multi-bit width and lower-speed data before it can be processed in the programmable device

This adds two major difficulties to the actual circuit design: First, after the high-speed serial data is converted into multi-bit width lower-speed data, the fan-out of some circuits will be greatly increased, and too much fan-out will affect the performance of the circuit. The maximum operating frequency that can be achieved; the second is that the 16 channels of data are independent of each other based on the transceiver integrated in the programmable device to achieve serial-to-parallel conversion, which greatly increases the amount of skew between data channels

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