Gate associated transistor with grooved gate polysilicon structure

Abstract

The invention relates to a gate associated transistor with a grooved gate polysilicon structure, wherein the upper surface of a silicon substrate slice taking a first conductivity type low-resistivity layer as a lower layer and a first conductivity type high-resistivity layer as an upper layer is provided with a plurality of first conductivity type emitter regions with high doping concentration, and the emitter regions are connected with doped polysilicon layers. The gate associated transistor is characterized in that the junction depths of the emitter regions are more than 1mu m, and the junction depths of base regions are between 4.5 and 8mu m; the junction depths of grooved gate regions are between 6.5 and 12mu m; and the ratio of a distance L between junctures of the two adjacent grooved gate regions with high doping concentration and the base regions to the difference D of the distance from the bottoms of the grooved gate regions to the upper surface of the silicon substrate slice and the junction depths of the base regions is that L / D is less than 1.8. The gate associated transistor has the advantages that the ability for resisting avalanche breakdown is strengthened, the failure rate in application is reduced by 1 to 2 orders of magnitude; and the gate associated transistor has remarkable functions of low cost and high performance-price ratio.

Description

technical field [0001] The invention relates to a connected gate transistor, which belongs to the technical field of silicon semiconductor devices. Background technique [0002] In 1979, Hisao Kondo proposed the gate associated transistor GAT (Gate Associated Transistor), followed by a detailed analysis (see IEEE Trans. Electron Device, vol. ED-27, PP.373-379.1980). In 1994, Chen Fuyuan, Jin Wenxin, and Wu Zhonglong made a further analysis of the gate transistor GAT (see "Power Electronics Technology", No. 4, 1994, 1994.11.pp52-55), pointing out that the gate transistor device exhibits high withstand voltage, Excellent characteristics such as fast switching and low saturation voltage drop. [0003] The early connected-gate transistors GAT all adopt planar structure. In 2000, Chinese invention patent ZL00100761.0 (hereinafter referred to as prior art 1) proposed a multi-gate transistor with a groove gate polysilicon structure, and the principle of its structure is as follow...

AI Technical Summary

Problems solved by technology

[0010] In the embodiment of prior art 1, P + The junction depth of the high-concentration trench gate region is 3-6 μm, which is shallow, resulting in poor resistance to avalanche breakdown.

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