Instruction combination filtration method and system for instruction grade stochastic verification

Abstract

The invention relates to an instruction combination filtering method and a system thereof which are used for instruction-level random verification. The method comprises the following steps: step 1, relevant constraints of the instruction combination to be filtered are added to instruction templates and the constraints comprise type definition of the instruction combination; step 2, the instruction filter is set to be in the FIFO queue mode; step 3, if the instruction combination entering the filter instruction queue is matched with the constraints, the instruction first entering the instruction queue of the instruction filter is deleted; otherwise, the instruction first entering the instruction queue of the instruction filter is output. The invention has the advantages of effectively solving the problem of flexible instruction combination filtering in random verification of large scale integrated circuits, meeting requirement of the debugging process with simplification design errors during verification of complex integrated circuits, preventing the test vectors from repeatedly covering design function points to be verified and the like, thereby better supporting the verification of complex integrated circuits.

Description

technical field [0001] The invention relates to the field of VLSI design verification, in particular to an instruction combination filtering method and system for instruction-level random verification. Background technique [0002] Functional verification is considered to be the bottleneck in the current hardware design process. In fact, in the entire design process, about 70% of the time and resources are spent on functional verification. Finding as many errors as possible has always been the focus of attention in the field of verification. [0003] Functional verification methods are mainly divided into two categories: simulation methods and formal methods. The application of formal methods is largely limited by the design scale; while simulation methods can handle large-scale integrated circuit design, especially contemporary complex high-performance processors, and are currently the main method for processor function verification. There are three main sources of the la...

AI Technical Summary

Problems solved by technology

[0014] In order to solve the above-mentioned technical problems, a method and system for instruction combination filtering for instruction-level random verification are provided. The practical needs of complex integrated circuit verification such as the debugging process and avoiding repeated coverage of test vectors to verify design function points

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