Circuit and method for reducing SRAM power consumption

Abstract

The invention provides a circuit for reducing SRAM power consumption and method thereof, the circuit comprises a reading and writing access unit for performing reading and writing operations to the SRAM and outputting a triggering signal; a low power consumption mode control unit for receiving the triggering signal of the reading and writing access unit and generating a clock switch signal; a clock switch unit for receiving the clock switch signal and performing the clock switch for the SRAM. The invention provides a high frequency clock for the SRAM when performing the reading and writing operations; switches the clock to low frequency when closing the reading and writing operations for the SRAM, and realizes that the SRAM can enter into the low power consumption mode and can be awaken quickly.

Description

technical field [0001] The invention relates to the field of SRAM control, in particular to a circuit and method for reducing SRAM power consumption. Background technique [0002] As an embedded application, the development trend of memory is to develop in three directions: smaller area, more power saving, and higher efficiency. In addition to flash memory, the largest usage is as a cache commonly used in SOC (System On Chip, multi-processor system-on-chip) and semiconductor chip products, with SRAM (Static Random-Access Memory, static random access memory) as the mainstream. With the improvement and development of process integration technology, the current trend of the semiconductor industry to manufacture integrated circuits is to use single-transistor architecture memory, that is, 1T SRAM. Due to its low cost and small chip area, it is conducive to greatly expanding capacity. Therefore, in It has been widely used in SOC system. However, the power consumption of SRAM is...

AI Technical Summary

Problems solved by technology

However, turning off the block power supply may lead to the loss of data in the closed block, and if the program suddenly has a large number of cache read and write requirements, it may be due to too many closed blocks, resulting in insufficient cache capacity, making it necessary to The number of repeated reads and writes increases, but increases power consumption

Moreover, SRAM requires a long delay to enter and exit low-power mode, which affects the bandwidth of SRAM

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