Manufacturing method of gate

Abstract

A method for making a grid electrode comprises the following steps that: a semiconductor substrate is provided with a multicrystal silicon layer; a metal layer is formed on the multicrystal silicon layer; visualization of the metal layer is carried out, and a grid electrode pattern is formed inside the metal layer; the multicrystal silicon layer uncovered by the grid electrode pattern is etched; during the etching process, a polymer layer is formed on the sidewall of the multicrystal silicon layer covered by the grid electrode pattern; and the polymer layer is removed to carry out the annealing process of the semiconductor substrate. The sidewall of the grid electrode formed by the method has less surface roughness.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for manufacturing a gate. Background technique [0002] With the continuous development of semiconductor manufacturing technology, the line width of the gate, which is used to measure the technological level of semiconductor manufacturing technology, is getting smaller and smaller; at present, the line width of the gate can reach 65nm or even smaller. A small gate line width can reduce the driving voltage of the formed semiconductor device, thereby reducing power consumption; in addition, a small gate line width can also reduce the size of the formed semiconductor device, improve integration, and increase the power consumption per unit area. The number of semiconductor devices reduces the cost. [0003] Figures 1 to 3 It is a schematic cross-sectional view of corresponding structures in each step of a conventional gate manufacturing method. Such as...

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Problems solved by technology

[0012] In the manufacturing method of the gate in the Chinese patent application document, a gate with a smaller line width can be formed through a subtractive process, but the process of etching the gate layer 5 to form the gate 5a generally uses anisotropic plasma Dry etching, so that the profile of the sidewall of the formed gate 5a is as vertical as possible to the surface of the semiconductor substrate 7; but the plasma dry etching also makes the surface of the sidewall of the gate relatively rough, The rough surface will cause the leakage current of the formed semiconductor device to increase; especially for the semiconductor device with a small gate line width, the leakage current is more sensitive to the roughness of the gate surface

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